公开(公告)号：US20240222291A1

公开(公告)日：2024-07-04

申请号：US18603174

申请日：2024-03-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/488 ,  H01L23/538

CPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/31 ,  H01L23/488 ,  H01L23/5384 ,  H01L24/14

摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US11581268B2

公开(公告)日：2023-02-14

申请号：US17542527

申请日：2021-12-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/76 ,  H01L21/768 ,  H01L23/31 ,  H01L23/488 ,  H01L23/538 ,  H01L23/00

摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US20200266076A1

公开(公告)日：2020-08-20

申请号：US16863518

申请日：2020-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Wei Chiu ,  Cheng-Hsien Hsieh ,  Hsien-Pin Hu ,  Kuo-Ching Hsu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L21/48 ,  H01L21/683 ,  H01L23/498

摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

公开(公告)号：US20200058616A1

公开(公告)日：2020-02-20

申请号：US16661636

申请日：2019-10-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538

摘要： An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

公开(公告)号：US20190221445A1

公开(公告)日：2019-07-18

申请号：US16362012

申请日：2019-03-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Wei Chiu ,  Cheng-Hsien Hsieh ,  Hsien-Pin Hu ,  Kuo-Ching Hsu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC分类号： H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13 ,  H01L2224/73204

摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

公开(公告)号：US20190115299A1

公开(公告)日：2019-04-18

申请号：US16206850

申请日：2018-11-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/306 ,  H01L23/14 ,  H01L23/495 ,  H01L23/532 ,  H01L21/48

摘要： An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.

公开(公告)号：US20180330969A1

公开(公告)日：2018-11-15

申请号：US16041904

申请日：2018-07-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Lai Wei Chih

IPC分类号： H01L21/56 ,  H01L21/78

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

摘要： Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer.

公开(公告)号：US10109607B2

公开(公告)日：2018-10-23

申请号：US15722578

申请日：2017-10-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Yu Chen ,  Hsien-Wei Chen ,  An-Jhih Su ,  Cheng-Hsien Hsieh

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/768

摘要： A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.

公开(公告)号：US20170250138A1

公开(公告)日：2017-08-31

申请号：US15170653

申请日：2016-06-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Tsung-Shu Lin

IPC分类号： H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014

摘要： An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

公开(公告)号：US20170033090A1

公开(公告)日：2017-02-02

申请号：US14815388

申请日：2015-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Hsien-Wei Chen ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Wei-Cheng Wu

IPC分类号： H01L25/10 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L24/19 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1041 ,  H01L2924/18162

摘要： Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively. The first opening, the second opening, the third opening, and the fourth opening are physically separated from each other.

摘要翻译： 描述了包装结构及其形成方法。 在一个实施例中，封装结构包括嵌入密封剂中的集成电路管芯和密封剂上的再分配结构。 再分配结构包括远离密封剂和集成电路管芯的金属化层，以及远离密封剂和集成电路管芯以及金属化层的电介质层。 封装结构还包括在电介质层上的第一下金属化结构和附接到第一下金属化结构的表面贴装器件和/或集成无源器件（“SMD / IPD”）。 第一下金属化结构包括分别延伸穿过介电层的第一至第四开口的第一至第四延伸部分，分别延伸到金属化层的第一至第四图案。 第一开口，第二开口，第三开口和第四开口在物理上彼此分离。