公开(公告)号：US20200075574A1

公开(公告)日：2020-03-05

申请号：US16559923

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Anton J. DEVILLIERS ,  Kandabara TAPILY

IPC: H01L27/02 ,  H01L27/092

Abstract: A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.

公开(公告)号：US20240047342A1

公开(公告)日：2024-02-08

申请号：US17882821

申请日：2022-08-08

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Hiroaki NIIMI ,  Kandabara TAPILY ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN

IPC: H01L23/522 ,  H01L29/08 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L23/5226 ,  H01L29/0847 ,  H01L21/76879 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76224

Abstract: A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/ID structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier.

公开(公告)号：US20230352343A1

公开(公告)日：2023-11-02

申请号：US18308230

申请日：2023-04-27

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  David POWER ,  Eric Chih-Fang LIU ,  Anton J. DEVILLIERS ,  Kandabara TAPILY ,  Jodi GRZESKOWIAK ,  David CONKLIN ,  Michael MURPHY

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L23/5226

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

公开(公告)号：US20230036597A1

公开(公告)日：2023-02-02

申请号：US17878457

申请日：2022-08-01

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Paul GUTWIN ,  Subhadeep KAL ,  Kandabara TAPILY ,  Anton DEVILLIERS

IPC: H01L21/822 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

公开(公告)号：US20200006140A1

公开(公告)日：2020-01-02

申请号：US16453473

申请日：2019-06-26

Applicant: Tokyo Electron Limited

Inventor： Kandabara TAPILY ,  Jeffrey SMITH

IPC: H01L21/768 ,  H01L23/522

Abstract: In a method for processing a substrate, a conductive cap layer is selectively formed over a plurality of conductive structures that are positioned in a first dielectric layer. A second dielectric layer is selectively formed over the first dielectric layer. A third dielectric layer is selectively formed over the second dielectric layer. A fourth dielectric layer is then formed over the plurality of conductive structures and the third dielectric layer, and an interconnect structure is subsequently formed within the fourth dielectric layer. The interconnect structure includes a via structure that has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are surrounded by the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.

公开(公告)号：US20190198390A1

公开(公告)日：2019-06-27

申请号：US15850458

申请日：2017-12-21

Applicant: Tokyo Electron Limited

Inventor： Takeshi ITATANI ,  Tadahiro ISHIZAKA ,  Kandabara TAPILY ,  Kai-Hung YU ,  Wanjae PARK

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/687 ,  H01L21/02

Abstract: A removal method is provided for selectively removing a plurality of types of metal oxide films in a plurality of recesses formed in a substrate that is arranged in a processing chamber. The removal method includes repeatedly performing process steps of exposing the plurality of types of metal oxide films to BCl3 gas or a BCl3 gas plasma generated by introducing BCl3 gas, stopping introduction of the BCl3 gas and performing a purge process, exposing the plurality of types of metal oxide films and/or a plurality of types of metal films underneath the metal oxide films to one or more different plasmas, at least one of which is generated by introducing a single gas of an inert gas, and stopping introduction of the inert gas and performing the purge process.