公开(公告)号：US08669138B2

公开(公告)日：2014-03-11

申请号：US13549001

申请日：2012-07-13

申请人： Akinobu Shibuya ,  Koichi Takemura ,  Akira Ouchi ,  Tomoo Murakami

发明人： Akinobu Shibuya ,  Koichi Takemura ,  Akira Ouchi ,  Tomoo Murakami

IPC分类号： H01L21/60

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A substrate and a semiconductor chip are connected by means of flip-chip interconnection. Around connecting pads of the substrate and input/output terminals of the semiconductor chip, an underfill material is injected. The underfill material is a composite material of filler and resin. Also, a first main surface of the substrate, which is not covered with the underfill material, and the side surfaces of the semiconductor chip are encapsulated with a molding material. The molding material is a composite material of filler and resin. An integrated body of the substrate and the semiconductor chip, which are covered with the molding material, is thinned from above and below.

摘要翻译： 衬底和半导体芯片通过倒装芯片互连连接。 在衬底的连接焊盘和半导体芯片的输入/输出端子之间，注入底部填充材料。 底部填充材料是填料和树脂的复合材料。 此外，未被底部填充材料覆盖的基板的第一主表面和半导体芯片的侧表面被模制材料封装。 成型材料是填料和树脂的复合材料。 由模制材料覆盖的衬底和半导体芯片的集成体从上方和下方变薄。

公开(公告)号：US08621730B2

公开(公告)日：2014-01-07

申请号：US13203018

申请日：2010-02-12

申请人： Akinobu Shibuya ,  Koichi Takemura ,  Takashi Manako

发明人： Akinobu Shibuya ,  Koichi Takemura ,  Takashi Manako

IPC分类号： H01G7/00

CPC分类号： H01G7/00 ,  H01L22/14 ,  H01L22/20 ,  H01L27/016 ,  H01L2924/0002 ,  Y10T29/43 ,  Y10T29/435 ,  H01L2924/00

摘要： In a capacitor producing method, a bottom electrode, a thin-film dielectric, and a top electrode are deposited on a substrate so as to form a capacitor, wherein defects including particles and electrical short-circuits between the bottom electrode and the top electrode are detected before the capacitor is divided into capacitor cells. Next, defects such as particles and electrical short-circuits between the bottom electrode and the top electrode are removed before the capacitor is divided into capacitor cells.

摘要翻译： 在电容器制造方法中，在基板上沉积底电极，薄膜电介质和顶电极以形成电容器，其中包括在底电极和顶电极之间的颗粒和电短路的缺陷是 在电容器分为电容器单元之前检测。 接下来，在将电容器分成电容器单元之前，去除在底部电极和顶部电极之间的诸如颗粒和电气短路的缺陷。

公开(公告)号：US06618694B1

公开(公告)日：2003-09-09

申请号：US09084108

申请日：1998-05-26

申请人： Akinobu Shibuya ,  Kouji Matsui ,  Hidehito Matsuyama

发明人： Akinobu Shibuya ,  Kouji Matsui ,  Hidehito Matsuyama

IPC分类号： G06F1750

CPC分类号： G06T17/20 ,  G06F17/5018 ,  G06F2217/80

摘要： A user uses part data forming means 101 and module data forming means 102 to input the actual dimension, physical constants and mesh dividing number for fundamental shapes which are registered in advance, thereby forming parts, and then indicates the relative position between the parts to form the entire shape of an assembly of plural parts without paying attention to coincidence or non-coincidence of nodal points. Data converting means 104 divides the shape of each part thus assembled according to the indicated mesh divisional number to generate element data and nodal point data. Further, it generates a constraint equation for connecting nodal points which are non-connected between neighboring parts, and forms an analysis model 401. A finite element method analyzer 105 uses approximate calculation means 106 to approximate a non-connected nodal point displacement from a nodal point displacement of neighboring structural elements on the basis of the constraint equation.

摘要翻译： 用户使用部件数据形成装置101和模块数据形成装置102输入预先登记的基本形状的实际尺寸，物理常数和网格划分数，从而形成零件，然后指示部件之间的相对位置，以形成 多个部分的组合的整体形状，而不注意节点的巧合或非重合。 数据转换装置104根据指示的网格划分数来划分如此组装的每个部分的形状，以生成元素数据和节点数据。 此外，它产生用于连接在相邻部分之间不连接的节点的约束方程，并且形成分析模型401.有限元方法分析器105使用近似计算装置106近似来自节点的非连接节点位移 基于约束方程的相邻结构元素的点位移。

公开(公告)号：US5485352A

公开(公告)日：1996-01-16

申请号：US358196

申请日：1994-12-16

申请人： Akinobu Shibuya ,  Mitsuru Kimura

发明人： Akinobu Shibuya ,  Mitsuru Kimura

IPC分类号： H01L23/12 ,  H01L23/498 ,  H05K3/24 ,  H05K1/09

CPC分类号： H05K3/246 ,  H01L23/49811 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092

摘要： An element joining pad for a semiconductor device mounting board includes a thick-film metalized layer, a barrier layer, and a Ni plating layer. The thick-film metalized layer is selectively formed on a low-temperature sintered board and consists of one of a metal and an alloy which can be sintered at 500.degree. C. or more and 1,200.degree. C. or less. The barrier layer is formed on the thick-film metalized layer and constituted by one of a Rh plating layer and a Ru plating layer. The Ni plating layer is formed on the barrier layer.

摘要翻译： 用于半导体器件安装板的元件接合焊盘包括厚膜金属化层，阻挡层和Ni镀覆层。 厚膜金属化层选择性地形成在低温烧结板上，由金属和合金之一组成，可以在500℃以上1200℃以下烧结。 阻挡层形成在厚膜金属化层上，由Rh镀层和Ru镀层之一构成。 在阻挡层上形成Ni镀层。

公开(公告)号：US20110302753A1

公开(公告)日：2011-12-15

申请号：US13203018

申请日：2010-02-12

申请人： Akinobu Shibuya ,  Koichi Takemura ,  Takashi Manako

发明人： Akinobu Shibuya ,  Koichi Takemura ,  Takashi Manako

IPC分类号： H01G7/00

CPC分类号： H01G7/00 ,  H01L22/14 ,  H01L22/20 ,  H01L27/016 ,  H01L2924/0002 ,  Y10T29/43 ,  Y10T29/435 ,  H01L2924/00

摘要： In a capacitor producing method, a bottom electrode, a thin-film dielectric, and a top electrode are deposited on a substrate so as to form a capacitor, wherein defects including particles and electrical short-circuits between the bottom electrode and the top electrode are detected before the capacitor is divided into capacitor cells. Next, defects such as particles and electrical short-circuits between the bottom electrode and the top electrode are removed before the capacitor is divided into capacitor cells.

摘要翻译： 在电容器制造方法中，在基板上沉积底电极，薄膜电介质和顶电极以形成电容器，其中包括在底电极和顶电极之间的颗粒和电短路的缺陷是 在电容器分为电容器单元之前检测。 接下来，在将电容器分成电容器单元之前，去除在底部电极和顶部电极之间的诸如颗粒和电气短路的缺陷。

公开(公告)号：US20100308474A1

公开(公告)日：2010-12-09

申请号：US12526236

申请日：2008-02-29

申请人： Akinobu Shibuya ,  Koichi Takemura ,  Akira Ouchi ,  Tomoo Murakami

发明人： Akinobu Shibuya ,  Koichi Takemura ,  Akira Ouchi ,  Tomoo Murakami

IPC分类号： H01L23/488 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A substrate (1) and a semiconductor chip (5) are connected by means of flip-chip interconnection. Around connecting pads (3) of the substrate (1) and input/output terminals (10) of the semiconductor chip (5), an underfill material (7) is injected. The underfill material (7) is a composite material of filler and resin in which the maximum particle diameter of the filler is 5 μm or below and whose filler content is 40 to 60 wt %. Also, a first main surface of the substrate (1), which is not covered with the underfill material (7), and the side surfaces of the semiconductor chip (5) are encapsulated with a molding material (8). The molding material (8) is a composite material of filler and resin whose filler content is over 75 wt % and in which the glass transition temperature of the resin is over 180° C. An integrated body of the substrate (1) and the semiconductor chip (5), which are covered with the molding material (8), is thinned from above and below.

摘要翻译： 基板（1）和半导体芯片（5）通过倒装芯片互连连接。 在衬底（1）的连接焊盘（3）和半导体芯片（5）的输入/输出端子（10）之间，注入底部填充材料（7）。 底部填充材料（7）是填料和树脂的复合材料，其中填料的最大粒径为5μm以下，填料的含量为40〜60重量％。 此外，未被底部填充材料（7）覆盖的基板（1）的第一主表面和半导体芯片（5）的侧表面被模制材料（8）封装。 成型材料（8）是填料和树脂的复合材料，其填料含量超过75重量％，树脂的玻璃化转变温度超过180℃。基板（1）和半导体 由模制材料（8）覆盖的芯片（5）从上方和下方变薄。

公开(公告)号：US06466124B1

公开(公告)日：2002-10-15

申请号：US09546334

申请日：2000-04-10

申请人： Akinobu Shibuya ,  Koji Matsui

发明人： Akinobu Shibuya ,  Koji Matsui

IPC分类号： H01C1012

CPC分类号： H01L28/24 ,  H01C7/006 ,  H01C7/06 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/167 ,  H05K3/4644 ,  H01L2924/00

摘要： There is provided a thin film resistor formed of titanium nitride containing oxygen in a solid solution condition.

摘要翻译： 提供了由固溶体状态的含有氮的氮化钛构成的薄膜电阻体。

公开(公告)号：US06278153B1

公开(公告)日：2001-08-21

申请号：US09420561

申请日：1999-10-19

申请人： Katsumi Kikuchi ,  Tadanori Shimoto ,  Koji Matsui ,  Akinobu Shibuya

发明人： Katsumi Kikuchi ,  Tadanori Shimoto ,  Koji Matsui ,  Akinobu Shibuya

IPC分类号： H01L27108

CPC分类号： H01L28/55 ,  H01L21/3212 ,  H01L21/76877 ,  H01L28/75 ,  H05K1/162

摘要： There is provided a thin film capacitor including (a) a lower electrode, (b) an insulating layer formed burying the lower electrode therein and formed with a via-hole reaching the lower electrode, (c) a dielectric layer formed on an inner sidewall of the via-hole and covering an exposed surface of the lower electrode therewith, and (d) an upper electrode surrounded by the dielectric layer. In accordance with the thin film capacitor, the upper electrode is formed to be buried in the via-hole formed above the lower electrode. Hence, it is possible to prevent short-circuit between the upper and lower electrodes, and degradation of the dielectric layer during fabrication of a thin film capacitor, both of which enhances reliability of a capacitor. In addition, a multi-layered wiring structure could be readily fabricated on the thin film capacitor.

摘要翻译： 提供一种薄膜电容器，其包括（a）下电极，（b）在其中埋设下电极并形成有到达下电极的通孔形成的绝缘层，（c）形成在内侧壁上的电介质层 的通孔，并且覆盖下电极的暴露表面，以及（d）由电介质层包围的上电极。 根据薄膜电容器，上电极被形成为埋在形成在下电极上的通孔中。 因此，可以防止上下电极之间的短路，以及薄膜电容器的制造时的电介质层的劣化，这两者都提高了电容器的可靠性。 此外，可以容易地在薄膜电容器上制造多层布线结构。

公开(公告)号：US08802496B2

公开(公告)日：2014-08-12

申请号：US13958989

申请日：2013-08-05

申请人： Akinobu Shibuya ,  Akira Ouchi

发明人： Akinobu Shibuya ,  Akira Ouchi

IPC分类号： H01L21/56

CPC分类号： H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0242 ,  H05K1/0243 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/10674 ,  H01L2924/00

摘要： Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

摘要翻译： 公开了一种用于半导体封装的衬底，其中可以防止辐射噪声从半导体元件和安装衬底之间的间隙泄漏。 用于半导体封装的衬底包括共面波导，其包括安装衬底上的信号和接地电极，连接到半导体元件的信号电极倒装芯片，布置在信号电极的两侧上的接地电极，间隔。 在半导体元件的安装区域的外周部的接地电极中形成台阶部，台阶部在安装基板的上表面与安装区域的外周部的接地电极之间具有较大的距离 形成安装区域的距离，并且形成用于覆盖安装区域的外周部分中的信号电极的绝缘体。

公开(公告)号：US08237292B2

公开(公告)日：2012-08-07

申请号：US12526236

申请日：2008-02-29

申请人： Akinobu Shibuya ,  Koichi Takemura ,  Akira Ouchi ,  Tomoo Murakami

发明人： Akinobu Shibuya ,  Koichi Takemura ,  Akira Ouchi ,  Tomoo Murakami

IPC分类号： H01L23/488

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A substrate (1) and a semiconductor chip (5) are connected by means of flip-chip interconnection. Around connecting pads (3) of the substrate (1) and input/output terminals (10) of the semiconductor chip (5), an underfill material (7) is injected. The underfill material (7) is a composite material of filler and resin in which the maximum particle diameter of the filler is 5 μm or below and whose filler content is 40 to 60 wt %. Also, a first main surface of the substrate (1), which is not covered with the underfill material (7), and the side surfaces of the semiconductor chip (5) are encapsulated with a molding material (8). The molding material (8) is a composite material of filler and resin whose filler content is over 75 wt % and in which the glass transition temperature of the resin is over 180° C. An integrated body of the substrate (1) and the semiconductor chip (5), which are covered with the molding material (8), is thinned from above and below.

摘要翻译： 基板（1）和半导体芯片（5）通过倒装芯片互连连接。 在衬底（1）的连接焊盘（3）和半导体芯片（5）的输入/输出端子（10）之间，注入底部填充材料（7）。 底部填充材料（7）是填料和树脂的复合材料，其中填料的最大粒径为5μm以下，填料含量为40〜60重量％。 此外，未被底部填充材料（7）覆盖的基板（1）的第一主表面和半导体芯片（5）的侧表面被模制材料（8）封装。 成型材料（8）是填料和树脂的复合材料，其填料含量超过75重量％，树脂的玻璃化转变温度超过180℃。基板（1）和半导体 由模制材料（8）覆盖的芯片（5）从上方和下方变薄。