公开(公告)号：US09601600B2

公开(公告)日：2017-03-21

申请号：US14855793

申请日：2015-09-16

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Cho-Han Fan ,  Chien-Ting Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.

公开(公告)号：US09583600B1

公开(公告)日：2017-02-28

申请号：US14877950

申请日：2015-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/283 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3213

CPC classification number: H01L29/785 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/32131 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and shallow trench isolation (STI) around the fin-shaped structure; forming a gate line across the fin-shaped structure and on the STI; performing a first cutting process to remove the part of the gate line directly above the fin-shaped structure and the fin-shaped structure directly under the gate line; and performing a second cutting process to remove part of the gate line on the STI.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的衬底和围绕鳍状结构的浅沟槽隔离（STI）; 在鳍状结构和STI上形成栅极线; 执行第一切割处理以直接在栅极线下方去除鳍状结构正上方的栅极线的一部分和鳍状结构; 并执行第二切割处理以去除STI上的栅极线的一部分。

公开(公告)号：US20170047426A1

公开(公告)日：2017-02-16

申请号：US15335418

申请日：2016-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L29/08

CPC classification number: H01L29/66598 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

Abstract: A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.

Abstract translation: 互补金属氧化物半导体场效应晶体管（MOSFET）包括衬底，第一MOSFET和第二MOSFET。 第一MOSFET设置在第一晶体管区域内的衬底上，并且第二MOSFET设置在第二晶体管区域内的衬底上。 第一MOSFET包括第一鳍结构，两个第一轻掺杂区，两个第一掺杂区和第一栅结构。 第一翅片结构包括第一主体部分和两个第一外延部分，其中每个第一外延部分设置在第一主体部分的每一侧上。 第一垂直接口位于第一主体部分和第一外延部分之间，使得第一轻掺杂区域能够均匀分布在每个第一垂直界面的整个表面上。

公开(公告)号：US09553026B1

公开(公告)日：2017-01-24

申请号：US14960447

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chien-Ting Lin ,  Li-Chiang Chen ,  Jyh-Shyang Jenq

IPC: H01L21/30 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first mandrel, a second mandrel, a third mandrel, and a fourth mandrel are formed on the substrate. Preferably, the first mandrel and the second mandrel include a first gap therebetween, the second mandrel and the third mandrel include a second gap therebetween, and the third mandrel and the fourth mandrel include a third gap therebetween, in which the first gap is equivalent to the third gap but different from the second gap. Next, spacers are formed adjacent to the first mandrel, the second mandrel, the third mandrel, and the fourth mandrel, and the spacers in the first gap and the third gap are removed.

Abstract translation: 公开了半导体器件的制造方法。 首先，设置基板，在基板上形成第一芯轴，第二心轴，第三心轴，第四心轴。 优选地，第一心轴和第二心轴包括其间的第一间隙，第二心轴和第三心轴在其间包括第二间隙，并且第三心轴和第四心轴在其间包括第三间隙，其中第一间隙等于 第三个差距，但与第二个差距不同。 接下来，在第一心轴，第二心轴，第三心轴和第四心轴附近形成间隔物，并且去除第一间隙和第三间隙中的间隔物。

公开(公告)号：US09455176B2

公开(公告)日：2016-09-27

申请号：US15072370

申请日：2016-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Lung-En Kuo ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.

Abstract translation: 本发明提供一种半导体结构，其包括基板，至少一个翅片组和设置在基板上的多个亚翅片结构，其中，翅片组设置在两个子鳍结构之间，并且每个子鳍结构的顶表面， 翅片结构低于翅片组的顶面; 以及设置在衬底中的浅沟槽隔离（STI），其中子鳍结构被浅沟槽隔离完全覆盖。

公开(公告)号：US09318609B2

公开(公告)日：2016-04-19

申请号：US14620209

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面。 第一顶面高于第二顶面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

公开(公告)号：US20160035854A1

公开(公告)日：2016-02-04

申请号：US14881162

申请日：2015-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

公开(公告)号：US20150380319A1

公开(公告)日：2015-12-31

申请号：US14847015

申请日：2015-09-08

Applicant: United Microelectronics Corp.

Inventor： Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

Abstract translation: 鳍状场效应晶体管工艺包括以下步骤。 提供基板。 第一鳍状场效应晶体管和第二鳍状场效应晶体管形成在基板上，其中第一鳍状场效应晶体管包括第一金属层和第二鳍状场效应晶体管 包括第二金属层。 对第一鳍状场效应晶体管进行处理处理，以调整第一鳍状场效应晶体管的阈值电压。 还提供了通过所述方法形成的鳍状场效应晶体管。

公开(公告)号：US09196542B2

公开(公告)日：2015-11-24

申请号：US13899581

申请日：2013-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin

IPC: H01L21/8234 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.

Abstract translation: 提供一种制造半导体器件的方法。 形成第一堆叠结构和第二堆叠结构以分别覆盖第一鳍结构和第二鳍结构的一部分。 随后，通过原子层沉积工艺分别在翅片结构的侧壁上形成间隔物，间隔物的组成包括硅氮化硅。 之后，形成并蚀刻层间电介质，以露出硬掩模层。 形成掩模层以覆盖第二堆叠结构和介电层的一部分。 之后，在掩模层的覆盖下去除第一堆叠结构中的硬掩模层。 然后，第一堆叠结构中的虚设层被导电层代替。

公开(公告)号：US09196500B2

公开(公告)日：2015-11-24

申请号：US13859720

申请日：2013-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Chien-Ting Lin

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/66795

Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.

Abstract translation: 一种用于制造半导体结构的方法，包括提供具有多个心轴图案和多个虚拟图案的基板，同时在心轴图案的侧壁上形成多个第一间隔件，在虚设图案的侧壁上形成多个第二间隔件，以及 移除第二间隔件和心轴图案以在基底上形成多个间隔图案。