公开(公告)号：US12249647B2

公开(公告)日：2025-03-11

申请号：US17702831

申请日：2022-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Chang ,  Shen-De Wang ,  Cheng-Hua Yang ,  Linggang Fang ,  Jianjun Yang ,  Wei Ta

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.

公开(公告)号：US11631766B2

公开(公告)日：2023-04-18

申请号：US17227392

申请日：2021-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

公开(公告)号：US10651183B1

公开(公告)日：2020-05-12

申请号：US16221382

申请日：2018-12-14

Applicant: United Microelectronics Corp.

Inventor： Jianjun Yang ,  Cheng-Hua Yang ,  Fan-Chi Meng ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L21/336 ,  H01L27/11517

Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.

公开(公告)号：US20170141200A1

公开(公告)日：2017-05-18

申请号：US14944224

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Shen-De Wang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Aaron Chen

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/265 ,  H01L21/321 ,  H01L27/115 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/788 ,  H01L29/51 ,  H01L29/66 ,  H01L21/223

CPC classification number: H01L29/42328 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28562 ,  H01L21/31111 ,  H01L21/321 ,  H01L21/32133 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

公开(公告)号：US20150270277A1

公开(公告)日：2015-09-24

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  ZHEN CHEN ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Wei Ta

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract translation: 本发明提供了一种存储单元，其包括基板，栅极介电层，图案化材料层，选择栅极和控制栅极。 栅介电层设置在基板上。 图案化材料层设置在基底上，其中图案化材料层包括垂直部分和水平部分。 选择栅极设置在栅极电介质层和图案化材料层的垂直部分的一侧。 控制栅极设置在图案化材料层的水平部分上并且在垂直部分的另一侧，其中垂直部分在选择栅极的顶部上方突出。 本发明还提供了存储单元的另一实施例及其制造方法。

公开(公告)号：US20230268437A1

公开(公告)日：2023-08-24

申请号：US17702831

申请日：2022-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Chang ,  Shen-De Wang ,  Cheng-Hua Yang ,  LINGGANG FANG ,  JIANJUN YANG ,  Wei Ta

IPC: H01L29/78 ,  H01L29/788 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/788 ,  H01L29/42328 ,  H01L27/088 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/66689 ,  H01L29/6656

Abstract: A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.

公开(公告)号：US20230215946A1

公开(公告)日：2023-07-06

申请号：US18120995

申请日：2023-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/42368 ,  H01L29/402 ,  H01L29/1095

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

公开(公告)号：US10192874B2

公开(公告)日：2019-01-29

申请号：US15626179

申请日：2017-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/423

Abstract: A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.

公开(公告)号：US20180342394A1

公开(公告)日：2018-11-29

申请号：US15603465

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi Qiang Mu ,  Chow Yee Lim ,  Hui Yang ,  YONG BIN FAN ,  JIANJUN YANG ,  Chih-Chien Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.

公开(公告)号：US10141194B1

公开(公告)日：2018-11-27

申请号：US15603465

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi Qiang Mu ,  Chow Yee Lim ,  Hui Yang ,  Yong Bin Fan ,  Jianjun Yang ,  Chih-Chien Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28273 ,  H01L21/02071 ,  H01L21/02074 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.