公开(公告)号：US11934106B2

公开(公告)日：2024-03-19

申请号：US17880700

申请日：2022-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Yen Liu ,  Hui-Fang Kuo ,  Chian-Ting Huang ,  Wei-Cyuan Lo ,  Yung-Feng Cheng ,  Chung-Yi Chiu

IPC: G03F7/00 ,  G03F1/36

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/705

Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

公开(公告)号：US20230411213A1

公开(公告)日：2023-12-21

申请号：US17868786

申请日：2022-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Ming-Chou Lu ,  Kun-Chen Ho ,  Dien-Yang Lu ,  Chun-Lung Chen ,  Chung-Yi Chiu

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/76832 ,  H01L21/7682 ,  H01L23/528 ,  H01L21/31116 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.

公开(公告)号：US20230403952A1

公开(公告)日：2023-12-14

申请号：US18239104

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10B63/00 ,  H10N70/011 ,  H10N70/231

Abstract: A memory device includes a substrate, a memory unit disposed on the substrate, a first spacer layer, and a second spacer layer. The memory unit includes a first electrode, a second electrode disposed above the first electrode, and a memory material layer disposed between the first electrode and the second electrode. The first spacer layer is disposed on a sidewall of the memory unit and includes a first portion disposed on a sidewall of the first electrode, a second portion disposed on a sidewall of the second electrode, and a bottom portion. A thickness of the second portion is greater than that of the first portion. The second spacer layer is disposed on the first spacer layer. A material composition of the second spacer layer is different from that of the first spacer layer. The bottom portion is disposed between the substrate and the second spacer layer.

公开(公告)号：US20230240161A1

公开(公告)日：2023-07-27

申请号：US17673812

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Chung-Yi Chiu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/16 ,  H01L45/146 ,  H01L45/1233

Abstract: A semiconductor memory device includes a substrate and a transistor disposed on the substrate. The transistor includes a source doped region, a drain doped region, a channel region, and a gate over the channel region. A data storage region is in proximity to the transistor and recessed into the substrate. The data storage region includes a ridge and a V-shaped groove. A bottom electrode layer conformally covers the ridge and V-shaped groove within the data storage region. A resistive-switching layer conformally covers the bottom electrode layer. A top electrode layer covers the resistive-switching layer.

公开(公告)号：US20220367192A1

公开(公告)日：2022-11-17

申请号：US17337457

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ying Lai ,  Hsin-Yu Hsieh ,  Chang-Mao Wang ,  Chung-Yi Chiu

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/3213

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.

公开(公告)号：US10199501B2

公开(公告)日：2019-02-05

申请号：US15678100

申请日：2017-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu

IPC: H01L21/321 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in the recess. The first epitaxial layer includes at least a second semiconductor material that a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. Subsequently, a thermal oxidation process is performed to the first epitaxial layer thereby forming a semiconductor layer at a bottom of the recess and a silicon oxide layer on the semiconductor layer. After removing the silicon oxide layer, a second epitaxial layer is formed on the semiconductor layer in the recess.

公开(公告)号：US09773910B2

公开(公告)日：2017-09-26

申请号：US14954967

申请日：2015-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/321 ,  H01L29/66 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/32105 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795

Abstract: A semiconductor structure includes a semiconductor substrate, at least a semiconductor layer formed on the semiconductor substrate, and at least a fin structure formed on the semiconductor layer. The semiconductor substrate includes a first semiconductor material, the semiconductor layer includes the first semiconductor material and a second semiconductor material, and the fin structure includes at least the first semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The semiconductor layer includes a first width, the fin structure includes a second width, and the second width is smaller than the first width.

公开(公告)号：US09722078B2

公开(公告)日：2017-08-01

申请号：US14855390

申请日：2015-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending downwardly from a top end and at least occupying 80% to 90% of the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

公开(公告)号：US09499399B2

公开(公告)日：2016-11-22

申请号：US13917655

申请日：2013-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

IPC: B81C1/00 ,  H01L21/302 ,  H01L21/461

CPC classification number: B81B3/0075 ,  B81B2207/07 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.

Abstract translation: 一种形成MEMS结构的方法，其中形成蚀刻停止层以埋入介电层内，并且在从背面蚀刻基板和介电层之间形成室时，蚀刻停止层 保护剩余的介电层。 如此形成的室在基板的背面具有开口，与开口相对的天花板和连接天花板的侧壁。 侧壁还可包括蚀刻停止层的一部分。

公开(公告)号：US09373719B2

公开(公告)日：2016-06-21

申请号：US14027334

申请日：2013-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Chung-Yi Chiu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/6681

Abstract: A semiconductor device is provided. The semiconductor device includes an active fin region, at least a gate strip, and a dummy fin region. The active fin region comprises at least an active fin. The gate strip is formed on the active fin region and extending across the active fin. The dummy fin region, comprising a plurality of dummy fins, is formed on two sides of the active fin region, and the dummy fins are formed on two sides of the gate strip.

Abstract translation: 提供半导体器件。 半导体器件包括有源鳍片区域，至少栅极条和伪鳍片区域。 活性鳍片区域至少包括活性鳍片。 栅极条形成在有源鳍片区域上并延伸穿过有源鳍片。 在活动鳍片区域的两侧形成有包括多个虚设翅片的虚拟鳍片区域，并且虚设翅片形成在栅极条的两侧。