公开(公告)号：US6136659A

公开(公告)日：2000-10-24

申请号：US47850

申请日：1998-03-25

申请人： Gunther Schindler ,  Walter Hartner ,  Volker Weinrich ,  Carlos Mazure-Espejo

发明人： Gunther Schindler ,  Walter Hartner ,  Volker Weinrich ,  Carlos Mazure-Espejo

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L21/20

CPC分类号： H01L28/65 ,  H01L21/32137

摘要： A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.

摘要翻译： 由铂金属形成的电容器电极的制造方法包括在具有用于电容器电极的含硅表面的基板上制造导电电极体。 铂在整个表面上沉积，铂在电极体外部的温度阶段被硅化，除去铂硅化物。 本发明的优点是避免金属铂的蚀刻工艺。

公开(公告)号：US06852240B2

公开(公告)日：2005-02-08

申请号：US09793350

申请日：2001-02-26

申请人： Walter Hartner ,  Günther Schindler ,  Volker Weinrich ,  Igor Kasko

发明人： Walter Hartner ,  Günther Schindler ,  Volker Weinrich ,  Igor Kasko

IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01G13/00

CPC分类号： H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.

摘要翻译： 铁电电容器配置配置有至少两个不同的强制电压。 首先产生具有形成至少两个层的表面的第一电极结构。 通过旋涂在第一电极上沉积不同厚度的铁电材料层。 随后在铁电材料层上形成第二电极结构。

公开(公告)号：US06730562B2

公开(公告)日：2004-05-04

申请号：US10364819

申请日：2003-02-11

申请人： Manfred Engelhardt ,  Walter Hartner ,  Frank Hintermaier ,  Günther Schindler ,  Volker Weinrich

发明人： Manfred Engelhardt ,  Walter Hartner ,  Frank Hintermaier ,  Günther Schindler ,  Volker Weinrich

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  H01L21/31122

摘要： A method for structuring ferroelectric layers on semiconductor substrates retains or regenerates the adherence and breakdown voltage resistance of the ferroelectric layer, which is especially significant for producing storage capacitors in large-scale integrated FeRAM and DRAM memory components. The addition of H2O or O2 results principally in the recovery of the electrostatic breakdown strength of the ferroelectric layer, which is of importance in particular when the ferroelectric serves as a dielectric of a storage capacitor and has to withstand electric fields of 5-10×106 V/m without a significant leakage current.

摘要翻译： 用于在半导体衬底上构造铁电层的方法保留或再生强电介质层的粘附和耐击穿电压，这对于在大规模集成的FeRAM和DRAM存储器组件中产生存储电容器尤其重要。 H 2 O或O 2的添加主要导致铁电层的静电击穿强度的恢复，特别是当铁电体用作储能电容器的电介质并且必须承受5-10×10 6的电场时，这尤其重要 > V / m，没有明显的漏电流。

公开(公告)号：US06825116B2

公开(公告)日：2004-11-30

申请号：US09845405

申请日：2001-04-30

申请人： Gerhard Beitel ,  Mattias Ahlstedt ,  Walter Hartner ,  Günther Schindler ,  Marcus Kastner ,  Volker Weinrich

发明人： Gerhard Beitel ,  Mattias Ahlstedt ,  Walter Hartner ,  Günther Schindler ,  Marcus Kastner ,  Volker Weinrich

IPC分类号： H01L21302

CPC分类号： H01L28/55 ,  H01L21/31053 ,  H01L21/3212 ,  H01L27/10811 ,  H01L27/11507

摘要： A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying a sacrifice layer, and removing the structures and the sacrifice layer in a polishing step. The method has the advantage that the sacrifice layer surrounds the structures that must be removed and stabilizes them, so that the structures can be eroded slowly and successively in the subsequent polishing step without breaking off. This prevents a smearing of the material of the structures such as occurs given direct polishing without a sacrifice layer.

摘要翻译： 描述了从衬底去除结构的方法。 该方法包括提供具有必须去除的结构的基底，施加牺牲层，以及在抛光步骤中去除结构和牺牲层。 该方法的优点在于，牺牲层围绕必须被去除和稳定的结构，从而可以在随后的抛光步骤中缓慢且连续地腐蚀结构而不会断裂。 这样可以防止结构材料的污染，例如直接抛光而没有牺牲层。

公开(公告)号：US06790676B2

公开(公告)日：2004-09-14

申请号：US10204830

申请日：2002-12-05

申请人： Hans Cerva ,  Walter Hartner ,  Frank Hintermaier ,  Joachim Hoepfner ,  Guenther Schindler ,  Volker Weinrich ,  Franz Winterauer

发明人： Hans Cerva ,  Walter Hartner ,  Frank Hintermaier ,  Joachim Hoepfner ,  Guenther Schindler ,  Volker Weinrich ,  Franz Winterauer

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/31691 ,  H01L27/11507 ,  H01L28/55

摘要： A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the ferroelectric layer, and changing the material into the ferroelectric layer by applying an outer electrical field aligned with the direction desired in the ferroelectric material and heat treating the material. By providing a first noble metal electrode on the surface before applying the material that is to become the ferroelectric layer and then subsequently forming a second noble metal electrode on the ferroelectric layer, a ferroelectric storage capacitor can be formed. If the substrate is provided with memory cells, which include at least one transistor for each cell and the above-mentioned ferroelectric storage capacitors, a ferroelectric memory arrangement can be produced.

摘要翻译： 一种铁电体层的制造方法，其特征在于，准备基板，涂敷随后转变为铁电体层的材料层，并且通过施加与铁电体中所需的方向对准的外部电场，将材料变更为铁电体层 材料和热处理材料。 通过在施加成为铁电体层的材料之后，在表面上设置第一贵金属电极，然后在铁电体层上形成第二贵金属电极，可以形成铁电存储电容器。 如果衬底设置有存储单元，其包括用于每个单元的至少一个晶体管和上述铁电存储电容器，则可以制造铁电存储器布置。

公开(公告)号：US06503792B2

公开(公告)日：2003-01-07

申请号：US09750531

申请日：2000-12-28

申请人： Walter Hartner ,  Günther Schindler ,  Volker Weinrich ,  Mattias Ahlstedt

发明人： Walter Hartner ,  Günther Schindler ,  Volker Weinrich ,  Mattias Ahlstedt

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  H01L21/3105 ,  H01L21/31122 ,  H01L21/32136 ,  H01L28/60

摘要： The damage to edge sections which occurs during the patterning of a metal-oxide-containing layer can be compensated by the deposition of an annealing layer and a subsequent heat treatment step through which a material flow takes place from the annealing layer into the damaged edge sections. The metal-oxide-containing layer can form the dielectric of a storage capacitor of a DRAM memory cell.

摘要翻译： 在含金属氧化物层的图案化期间发生的对边缘部分的损伤可以通过沉积退火层和随后的热处理步骤来补偿，通过该步骤将材料流从退火层发生到损坏的边缘部分 。 含金属氧化物的层可以形成DRAM存储单元的存储电容器的电介质。

公开(公告)号：US20140035154A1

公开(公告)日：2014-02-06

申请号：US13564922

申请日：2012-08-02

申请人： Ottmar Geitner ,  Walter Hartner ,  Maciej Wojnowski ,  Ulrich Wachter ,  Michael Bauer ,  Andreas Stueckjuergen

发明人： Ottmar Geitner ,  Walter Hartner ,  Maciej Wojnowski ,  Ulrich Wachter ,  Michael Bauer ,  Andreas Stueckjuergen

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L24/96 ,  H01L23/3128 ,  H01L23/49855 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/24051 ,  H01L2224/32245 ,  H01L2224/73151 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/142 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/13 ,  H01L2224/21 ,  H01L2924/00 ,  H01L2924/00014

摘要： A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.

摘要翻译： 提供了芯片封装，芯片封装包括：芯片，包括形成在芯片正面上的至少一个接触焊盘; 至少部分地围绕所述芯片并且覆盖所述至少一个接触垫的封装材料; 以及通过所述封装材料形成的至少一个电互连，其中所述至少一个电互连构造成将所述至少一个接触焊盘从所述芯片前侧的芯片封装第一侧电重定向到形成在所述芯片前侧上的至少一个焊料结构 芯片封装第二面在芯片背面。

公开(公告)号：US07468307B2

公开(公告)日：2008-12-23

申请号：US11476497

申请日：2006-06-28

申请人： Walter Hartner ,  Andreas Meiser ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Walter Hartner ,  Andreas Meiser ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L21/76

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/7809 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.

摘要翻译： 半导体结构包括半导体层堆叠，其包括第一导电类型的半导体衬底，第二导电类型的重掺杂掩埋层和形成在半导体层的顶部上的第三导电类型的单晶半导体层和埋入 层，与埋层的接触，在接触孔中形成的接触以及半导体结构的不同部分的横向绝缘，所述绝缘体形成在隔离沟槽中。 可以在隔离沟槽内形成与半导体衬底的接触。

公开(公告)号：US20070018195A1

公开(公告)日：2007-01-25

申请号：US11476497

申请日：2006-06-28

申请人： Walter Hartner ,  Andreas Meiser ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Walter Hartner ,  Andreas Meiser ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L29/74

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/7809 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.

摘要翻译： 半导体结构包括半导体层堆叠，其包括第一导电类型的半导体衬底，第二导电类型的重掺杂掩埋层和形成在半导体层的顶部上的第三导电类型的单晶半导体层和埋入 层，与埋层的接触，在接触孔中形成的接触以及半导体结构的不同部分的横向绝缘，所述绝缘体形成在隔离沟槽中。 可以在隔离沟槽内形成与半导体衬底的接触。

公开(公告)号：US20110256688A1

公开(公告)日：2011-10-20

申请号：US13156970

申请日：2011-06-09

申请人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L21/76

CPC分类号： H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.