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    MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    11.
    发明公开
    MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240179903A1

    公开(公告)日：2024-05-30

    申请号：US17993997

    申请日：2022-11-25

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Wei-Che Chang

    IPC: H01L27/11582 ,  H01L27/11565

    CPC classification number: H01L27/11582 ,  H01L27/11565

    Abstract: Provided is a flash memory device including a gate stack structure, at least three channel pillars, a charge storage structure, at least three source line, and at least three bit lines. The gate stack structure is disposed above a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately each other. The at least three channel pillars extend through the gate stack structure. The at least three channel pillars are electrically isolated from one another. The charge storage structure is disposed between the plurality of gate layers and the at least three channel pillars. The at least three source line are disposed below the gate stack structure and electrically connected to the at least three channel pillars. The at least three bit lines are disposed above the gate stack structure, and electrically connected to the at least three channel pillars.

    MEMORY DEVICE
    14.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20220076744A1

    公开(公告)日：2022-03-10

    申请号：US17012077

    申请日：2020-09-04

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Ping-Kun Wang ,  Kuang-Chih Hsieh ,  Chien-Min Wu ,  Meng-Hung Lin

    IPC: G11C13/00 ,  H01L45/00

    Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

    Patterning method
    15.
    发明授权
    Patterning method 有权

    公开(公告)号：US11024511B1

    公开(公告)日：2021-06-01

    申请号：US16853766

    申请日：2020-04-21

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen

    IPC: H01L21/308 ,  H01L21/027 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3213 ,  H01L29/66

    Abstract: Provided is a patterning method including: providing a strip layer with a plurality of strips A, in combination with a plurality of strips B and strips C arranged alternately between the strips A; forming a first mask layer having a first opening on the strip layer; removing the strips A and B exposed by the first opening; forming a plurality of first spacers on sidewalls defined by the first opening; forming a plurality of second spacers on sidewalls of the first spacers respectively; forming a second mask layer having a second opening on the strip layer; removing the strips A and C exposed by the second opening; forming a plurality of third spacers defined by the second opening; forming a plurality of fourth spacers on sidewalls of the third spacers respectively; and removing the strips A, the first spacers, and the third spacers to form a pattern layer.

    RESISTIVE RANDOM ACCESS MEMORY
    16.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20170279041A1

    公开(公告)日：2017-09-28

    申请号：US15076676

    申请日：2016-03-22

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen

    IPC: H01L45/00

    CPC classification number: H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1641

    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance changeable layer, an oxygen reservoir layer and a reactive oxygen barrier layer. The bottom electrode is disposed on a substrate. The top electrode is disposed above the bottom electrode. The resistance changeable layer is disposed between the bottom electrode and the top electrode. The oxygen reservoir layer is disposed between the resistance changeable layer and the top electrode. The reactive oxygen barrier layer is disposed inside the oxygen reservoir layer.

    RESISTIVE RANDOM ACCEESS MEMORY
    18.
    发明申请
    RESISTIVE RANDOM ACCEESS MEMORY 审中-公开
    电阻随机存储器

    公开(公告)号：US20160351623A1

    公开(公告)日：2016-12-01

    申请号：US14726626

    申请日：2015-06-01

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Ping-Kun Wang ,  Shao-Ching Liao

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/147

    Abstract: A resistive random access memory is provided. The resistive memory cell includes a substrate, a transistor on the substrate, a bottom electrode on the substrate and electrically connected to the transistor source/drain, several top electrodes on the bottom electrode, several resistance-switching layers between the top and bottom electrode, and several current limiting layers between the resistance-switching layer and top electrodes. The cell could improve the difficulty on recognizing 1/0 signal by current at high temperature environment and save the area on the substrate by generating several conductive filaments at one transistor location.

    Abstract translation: 提供了一种电阻式随机存取存储器。 电阻式存储单元包括衬底，衬底上的晶体管，衬底上的底部电极，并电连接到晶体管源极/漏极，底部电极上的几个顶部电极，顶部和底部电极之间的几个电阻切换层， 以及电阻切换层和顶部电极之间的若干电流限制层。 该电池可以提高在高温环境下通过电流识别1/0信号的难度，并通过在一个晶体管位置产生几个导电细丝来节省基板上的面积。

    RESISTIVE RANDOM ACCESS MEMORY
    19.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY 审中-公开
    电阻随机存取存储器

    公开(公告)号：US20160315255A1

    公开(公告)日：2016-10-27

    申请号：US15067184

    申请日：2016-03-11

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Ping-Kun Wang ,  Shao-Ching Liao ,  Meng-Hung Lin

    IPC: H01L45/00

    CPC classification number: H01L45/1266 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    Abstract: A resistive random access memory (RRAM) including a first electrode, a second electrode, and a variable-resistance oxide layer disposed between the first electrode and the second electrode is provided. The RRAM further includes an oxygen exchange layer, an oxygen-rich layer, and a first oxygen barrier layer. The oxygen exchange layer is disposed between the variable-resistance oxide layer and the second electrode. The oxygen-rich layer is disposed between the oxygen exchange layer and the second electrode. The first oxygen barrier layer is disposed between the oxygen exchange layer and the oxygen-rich layer.

    Abstract translation: 提供了包括设置在第一电极和第二电极之间的第一电极，第二电极和可变电阻氧化物层的电阻随机存取存储器（RRAM）。 RRAM还包括氧交换层，富氧层和第一氧阻隔层。 氧交换层设置在可变电阻氧化物层和第二电极之间。 富氧层设置在氧交换层和第二电极之间。 第一氧阻隔层设置在氧交换层和富氧层之间。

    Filament forming method for resistive memory unit
    20.
    发明授权
    Filament forming method for resistive memory unit 有权

    公开(公告)号：US11972799B2

    公开(公告)日：2024-04-30

    申请号：US17683356

    申请日：2022-03-01

    Applicant: Winbond Electronics Corp.

    Inventor： Frederick Chen ,  Ping-Kun Wang ,  Chia-Hung Lin ,  Jun-Yao Huang

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C2013/0045

    Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

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