公开(公告)号：US09602108B1

公开(公告)日：2017-03-21

申请号：US14852164

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young ,  Alireza S. Kaviani

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17728 ,  H03K19/0008 ,  H03K19/17744 ,  H03K19/1776

Abstract: In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.

公开(公告)号：US09509307B1

公开(公告)日：2016-11-29

申请号：US14492370

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Vikram Santurkar ,  Anil Kumar Kandala ,  Santosh Yachareni ,  Shidong Zhou ,  Robert Fu ,  Philip Costello ,  Sandeep Vundavalli ,  Steven P. Young ,  Brian C. Gaide

IPC: H03K19/003 ,  H03K19/173 ,  H03K19/00 ,  G11C7/12

CPC classification number: H03K19/003 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/417 ,  H03K19/0008 ,  H03K19/1737

Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Abstract translation: 互连多路复用器包括第一多路复用器级的多个CMOS通过门，其耦合以接收由互连多路复用器输出的数据; 输出反相器，其耦合到所述多个CMOS遍栅的输出，其中所述输出反相器的输出是所述互连多路复用器的输出; 以及耦合到所述多个CMOS通孔的多个存储元件; 其中在启动模式期间将多个CMOS通孔的输入拉至公共电位。 还公开了降低集成电路中的争用电流的方法。

公开(公告)号：US08773166B1

公开(公告)日：2014-07-08

申请号：US13666236

申请日：2012-11-01

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young

IPC: H03K19/0175

CPC classification number: H03K19/01759 ,  H03K19/01707

Abstract: An apparatus includes a first output stage and a first input stage of a first single track buffer, as well as a second output stage and a second input stage of a second single track buffer. The second single track buffer is downstream from the first single track buffer. The first output stage and the second input stage are coupled to one another via bidirectional rails. The first output stage and the second input stage in combination provide a first pulse generator.

Abstract translation: 一种装置包括第一单轨道缓冲器的第一输出级和第一输入级，以及第二单轨迹缓冲器的第二输出级和第二输入级。 第二单轨道缓冲器是从第一单轨道缓冲器的下游。 第一输出级和第二输入级通过双向导轨相互耦合。 第一输出级和第二输入级组合提供第一脉冲发生器。

公开(公告)号：US12271332B2

公开(公告)日：2025-04-08

申请号：US18128936

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Brian C. Gaide

IPC: G06F13/40 ,  H01L25/065 ,  H10B80/00

Abstract: A 3D stacked device includes a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips each include a plurality of portions grouped into slivers according to the column they lie in. Each of the portions further includes a plurality of blocks grouped into sub-slivers and interconnected by inter-block bridges. A block that must be functional on the bottommost chip of the 3D stacked device is configured to bypass a neighboring nonfunctional block on the same chip by using a communication path of an inter-block bridge to a neighboring functional block that is in the same sub-sliver as the nonfunctional block but in a different chip. So long as only one of the blocks in a sub-sliver is nonfunctional, the inter-block bridges permit the other blocks in the sub-sliver to receive and route data.

公开(公告)号：US11063594B1

公开(公告)日：2021-07-13

申请号：US16872009

申请日：2020-05-11

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

Abstract: An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.

公开(公告)号：US10715149B1

公开(公告)日：2020-07-14

申请号：US16513190

申请日：2019-07-16

Applicant: Xilinx, Inc.

Inventor： Eric F. Dellinger ,  Jay T. Young ,  Brian C. Gaide ,  Chirag Ravishankar ,  Davis Moore ,  Steven P. Young

IPC: H03K19/17736 ,  H03K19/17724

Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

公开(公告)号：US10320386B1

公开(公告)日：2019-06-11

申请号：US15836571

申请日：2017-12-08

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Brian C. Gaide ,  Henri Fraisse

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/20 ,  H03K19/0175 ,  H03K19/173 ,  H03K3/037 ,  H03K19/177

Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

公开(公告)号：US10284185B1

公开(公告)日：2019-05-07

申请号：US15845957

申请日：2017-12-18

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Ilya K. Ganusov ,  Chi M. Nguyen ,  Robert I. Fu

IPC: H03K5/15 ,  G06F1/10 ,  G06F1/12 ,  H03K19/096 ,  H03K5/00

Abstract: The disclosed circuit arrangements include a logic circuit, input register logic coupled to the logic circuit and including a first plurality of bi-stable circuits and a control circuit coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals from an input clock signal. The plurality of delayed clock signals include a first delayed clock signal and a second delayed clock signal. The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.

公开(公告)号：US10110202B1

公开(公告)日：2018-10-23

申请号：US15451778

申请日：2017-03-07

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  John G. O'Dwyer

IPC: H03K3/011 ,  H03K5/15 ,  H03K5/19 ,  H03K5/00

Abstract: An apparatus for clock deskew includes: a first delay element configured to receive a clock signal from a clock, wherein the delay element comprises multiple delay lines; a first multiplexer coupled to the multiple delay lines; a sensor configured to sense a voltage, a temperature, or both, and to provide a sensor output based at least on the sensed voltage and/or the sensed temperature; and a converter configured to receive the sensor output, and to generate a converted signal; wherein the first multiplexer is configured to provide a delay line output from one of the multiple delay lines based at least in part on the converted signal.

公开(公告)号：US09455714B1

公开(公告)日：2016-09-27

申请号：US14851577

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide

IPC: G06F15/00 ,  H03K19/177

CPC classification number: H03K19/17728 ,  H03K19/17744 ,  H03K19/1776

Abstract: In an example, a configurable logic element for a programmable integrated circuit (IC) includes a first lookup-table (LUT) including first inputs and first outputs, and first sum logic and first carry logic coupled between the first inputs and the first outputs; a second LUT including second inputs and second outputs, and second sum logic coupled between the second inputs and the second outputs; and first and second cascade multiplexers respectively coupled to the first and second LUTs, an input of the second cascade multiplexer coupled to an output of the first carry logic in the first LUT.

Abstract translation: 在一个示例中，用于可编程集成电路（IC）的可配置逻辑元件包括包括第一输入和第一输出的第一查找表（LUT）以及耦合在第一输入和第一输出之间的第一和逻辑和第一进位逻辑; 包括第二输入和第二输出的第二LUT和耦合在第二输入和第二输出之间的第二和逻辑; 以及分别耦合到第一和第二LUT的第一和第二级联多路复用器，耦合到第一LUT中的第一进位逻辑的输出的第二级联多路复用器的输入。