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129 条记录 (耗时 0.022 秒)

    Semiconductor integrated circuit memory
    12.
    发明授权
    Semiconductor integrated circuit memory 有权
    半导体集成电路存储器

    公开(公告)号：US06185149B2

    公开(公告)日：2001-02-06

    申请号：US09340147

    申请日：1999-06-28

    申请人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

    发明人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

    IPC分类号： G11C800

    CPC分类号： G11C7/1018 ,  G11C7/1072

    摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

    摘要翻译： 半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。

    Dynamic memory circuit with automatic refresh function
    15.
    发明授权
    Dynamic memory circuit with automatic refresh function 失效
    动态内存电路具有自动刷新功能

    公开(公告)号：US06438055B1

    公开(公告)日：2002-08-20

    申请号：US09688941

    申请日：2000-10-17

    申请人： Masao Taguchi ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Yasurou Matsuzaki

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： The present invention is that in a dynamic memory circuit, first and second internal operation cycles are assigned to one external operation cycle according to external commands, a memory core performs a read operation which corresponds to a read command at the first internal operation, and performs a refresh operation which responds to a refresh command at the second internal operation cycle. Also the memory core performs a refresh operation which responds to a refresh command at the first internal operation cycle, and performs a write operation which corresponds to a write command at the second internal operation cycle. It is preferable that when the read or write command is not input, the refresh operation is performed at the earlier internal operation cycle. And a refresh command generation circuit which generates the refresh command at a refresh time is created in the memory circuit.

    摘要翻译： 本发明是在动态存储电路中，根据外部指令将第一和第二内部动作周期分配给一个外部动作周期，在第一内部动作中，存储器核心进行与读出命令对应的读取动作， 在第二内部操作周期响应刷新命令的刷新操作。 此外，存储器核心执行在第一内部操作周期响应刷新命令的刷新操作，并且在第二内部操作周期执行与写入命令相对应的写入操作。 优选的是，当没有输入读取或写入命令时，在较早的内部操作周期执行刷新操作。 并且在存储器电路中创建在刷新时间产生刷新命令的刷新命令产生电路。

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    16.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06424199B1

    公开(公告)日：2002-07-23

    申请号：US09978022

    申请日：2001-10-17

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： H03K3013

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor device with circuitry for efficient information exchange
    17.
    发明授权
    Semiconductor device with circuitry for efficient information exchange 有权
    具有用于有效信息交换的电路的半导体器件

    公开(公告)号：US07782682B2

    公开(公告)日：2010-08-24

    申请号：US10006238

    申请日：2001-12-10

    申请人： Yasurou Matsuzaki ,  Masao Taguchi

    发明人： Yasurou Matsuzaki ,  Masao Taguchi

    IPC分类号： G11C7/77

    CPC分类号： H03M5/14 ,  G11C8/10 ,  H03M7/00 ,  H03M7/30

    摘要： A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.

    摘要翻译： 具有寄存器和信息产生电路的半导体器件可以减少要传输的数据，从而节省电力。 寄存器存储第一个信息。 信息生成电路响应于从设备的外部获取的信号，生成指示第一信息的哪些位将被反转的第二信息。

    Semiconductor device and multichip module
    19.
    发明授权
    Semiconductor device and multichip module 有权

    公开(公告)号：US06519171B2

    公开(公告)日：2003-02-11

    申请号：US09904478

    申请日：2001-07-16

    申请人： Yasurou Matsuzaki ,  Masao Taguchi

    发明人： Yasurou Matsuzaki ,  Masao Taguchi

    IPC分类号： G11C502

    CPC分类号： G11C7/10 ,  G11C29/48 ,  G11C2207/104

    摘要： A semiconductor memory device manufactured separately is connected to an interface unit of a semiconductor device. An internal memory formed in the semiconductor device is connected to at least a part of the interface unit. A memory selecting circuit makes the internal memory accessible in a first operation mode, and makes the internal memory inaccessible in a second operation mode. Therefore, for example, putting the semiconductor device into the first operation mode and accessing the internal memory enables the semiconductor device to operate as a predetermined system even when the semiconductor memory device is not connected to the interface unit. The substitution of the internal memory for the semiconductor memory device makes it possible for the semiconductor device to test the interface unit and associated circuits thereof by itself. This consequently allows improvement in the assembly yield of multichip modules.

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    20.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06225841B1

    公开(公告)日：2001-05-01

    申请号：US09556948

    申请日：2000-04-21

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： H03B1900

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.