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    MASK ROM DEVICES AND METHODS FOR FORMING THE SAME
    11.
    发明申请
    MASK ROM DEVICES AND METHODS FOR FORMING THE SAME 审中-公开
    掩模ROM器件及其形成方法

    公开(公告)号：US20100167487A1

    公开(公告)日：2010-07-01

    申请号：US12723265

    申请日：2010-03-12

    Applicant: Myung-Jo Chun ,  Hee-Seong Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

    Inventor： Myung-Jo Chun ,  Hee-Seong Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

    IPC: H01L21/336

    CPC classification number: H01L27/11293 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665

    Abstract: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

    Abstract translation: 掩模只读存储器（MROM）器件分别包括形成在衬底的单元和离子区域的第一和第二栅电极。 第一杂质区形成在基板的单电池区域上，以便与第一栅电极相邻。 形成与第一杂质区相同导电类型的第二杂质区，以与第二栅电极的侧壁间隔开。 第四杂质区形成在离电池区域，从第二杂质区延伸并与第二栅电极的侧壁重叠。 第四杂质区域具有与第二杂质区域相反的导电类型，并且深度大于第二杂质区域的深度。

    Non-volatile memory devices including local control gates on multiple isolated well regions and related methods and systems
    12.
    发明授权
    Non-volatile memory devices including local control gates on multiple isolated well regions and related methods and systems 有权
    非易失性存储器件包括多个隔离阱区域上的本地控制栅极以及相关的方法和系统

    公开(公告)号：US07733696B2

    公开(公告)日：2010-06-08

    申请号：US11818238

    申请日：2007-06-13

    Applicant: Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

    Inventor： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

    IPC: G11C11/34

    CPC classification number: G11C16/0433 ,  G11C8/10 ,  G11C16/08 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

    Abstract: A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.

    Abstract translation: 非易失性集成电路存储器件可以包括具有相同导电类型的第一和第二电隔离阱的半导体衬底。 可以在第一阱上提供第一多个非易失性存储单元晶体管，并且可以在第二阱上提供第二多个非易失性存储单元晶体管。 本地控制栅极线可以与第一和第二多个非易失性存储单元晶体管电耦合，并且组选择晶体管可以电耦合在本地控制栅极线和全局控制栅极线之间。 更具体地，组选择晶体管可以被配置为响应于施加到组选择晶体管的栅极的组选择栅极信号来电耦合和去耦合本地控制栅极线和全局控制栅极线。 还讨论了相关方法和系统。

    Methods of forming fin field effect transistors using oxidation barrier layers and related devices
    15.
    发明申请
    Methods of forming fin field effect transistors using oxidation barrier layers and related devices 有权
    使用氧化阻挡层和相关器件形成鳍式场效应晶体管的方法

    公开(公告)号：US20050272192A1

    公开(公告)日：2005-12-08

    申请号：US11020899

    申请日：2004-12-23

    Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

    Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786

    CPC classification number: H01L29/7854 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78645

    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

    Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

    Memory devices and methods of operating the same
    17.
    发明授权
    Memory devices and methods of operating the same 有权
    内存设备及操作方法

    公开(公告)号：US09418739B2

    公开(公告)日：2016-08-16

    申请号：US14616806

    申请日：2015-02-09

    Applicant: Yong-Kyu Lee ,  Yeong-Taek Lee

    Inventor： Yong-Kyu Lee ,  Yeong-Taek Lee

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/72

    Abstract: Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.

    Abstract translation: 操作存储设备的方法包括： 对连接到所选择的存储单元的所选择的第一信号线施加第一组写入电压，向连接到未选择的存储器单元的未选择的第一信号线施加第一抑制电压，以及控制所选择的第二信号线的第一电压 连接到所选择的存储单元以小于第一设置写入电压，并且第一抑制电压和第一电压之间的差小于选择元件的阈值电压。

    MAGNETIC MEMORY DEVICES INCLUDING SHARED LINES
    18.
    发明申请
    MAGNETIC MEMORY DEVICES INCLUDING SHARED LINES 有权
    包含共享线的磁记录设备

    公开(公告)号：US20150155024A1

    公开(公告)日：2015-06-04

    申请号：US14448717

    申请日：2014-07-31

    Applicant: Bo-Young SEO ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

    Inventor： Bo-Young SEO ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659

    Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

    Abstract translation: 磁存储器件包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。 磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。 还描述了相关系统和操作方法。

    Non-volatile memory device
    19.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08526231B2

    公开(公告)日：2013-09-03

    申请号：US13177873

    申请日：2011-07-07

    Applicant: Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    Inventor： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

    IPC: G11C11/34

    CPC classification number: G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

    Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

    Abstract translation: 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

    Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same
    20.
    发明申请
    Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same 有权
    电可擦除可编程只读存储器（EEPROM）单元及其形成和读取方法

    公开(公告)号：US20110038210A1

    公开(公告)日：2011-02-17

    申请号：US12912517

    申请日：2010-10-26

    Applicant: Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Jung-Ho Moon ,  Soung-Youb Ha

    Inventor： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Jung-Ho Moon ,  Soung-Youb Ha

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30

    CPC classification number: G11C16/0433 ,  G11C16/26 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    Abstract: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.

    Abstract translation: 在EEPROM单元中读取数据的方法中，用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。 第一电压被施加到存储晶体管的感测线。 大于第一电压的第二电压被施加到选择晶体管的字线。 将通过EEPROM单元的电流与预定的参考电流进行比较，以读取存储在EEPROM单元中的数据。 可以在擦除状态下增加EEPROM单元的通电池电流，并且可以容易地区分单元中的数据。

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