公开(公告)号：US20110008048A1

公开(公告)日：2011-01-13

申请号：US12662674

申请日：2010-04-28

Applicant: Yong-hoon Kim ,  Hee-Seok Lee

Inventor： Yong-hoon Kim ,  Hee-Seok Lee

IPC: H04B10/00 ,  H04J14/02

CPC classification number: H04J14/0283 ,  H04J14/0201

Abstract: An optical system and an SSD module that maintain optimal SI, PI and EMI characteristics without a shield based on a ground voltage and an impedance match. The optical system includes a solid state drive (SSD) module and an input/output (I/O) interface. The SSD module includes a plurality of solid state memory units. The input/output (I/O) interface receives data to be written to at least one of the solid state memory units from a main memory unit, the input/output (I/O) interface transmits data written in at least one of the solid state memory units to the main memory unit. The SSD module and the I/O interface transmit and receive data using an optical medium.

Abstract translation: 一种光学系统和一个SSD模块，可以根据接地电压和阻抗匹配保持最佳的SI，PI和EMI特性，而不需要屏蔽。 光学系统包括固态驱动器（SSD）模块和输入/输出（I / O）接口。 SSD模块包括多个固态存储器单元。 输入/输出（I / O）接口从主存储器单元接收要写入至少一个固态存储器单元的数据，输入/输出（I / O）接口发送写入至少一个 固态存储器单元到主存储器单元。 SSD模块和I / O接口使用光学介质发送和接收数据。

公开(公告)号：US20100013066A1

公开(公告)日：2010-01-21

申请号：US12568224

申请日：2009-09-28

Applicant: Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

Inventor： Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

IPC: H01L23/60 ,  H01L23/52

CPC classification number: H01L23/552 ,  H01L23/60 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip.

Abstract translation: 半导体封装包括主衬底，具有第一侧和第二侧的半导体芯片，设置在主衬底上并与主衬底电连接的半导体芯片的第一侧和形成在主衬底的第二侧上的导电网络 半导体芯片。

公开(公告)号：US20070164347A1

公开(公告)日：2007-07-19

申请号：US11623829

申请日：2007-01-17

Applicant: Yong-hoon Kim

Inventor： Yong-hoon Kim

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11519

Abstract: Non-volatile memory devices according to embodiments of the present invention include an EEPROM transistor in a first portion of a semiconductor substrate, an access transistor in a second portion of the semiconductor substrate and an erase transistor in a third portion of the semiconductor substrate. The second portion of the semiconductor substrate extends adjacent a first side of the first portion of the semiconductor substrate and the third portion of the semiconductor substrate extends adjacent a second side of the first portion of the semiconductor substrate. The first and second sides of the first portion of the semiconductor substrate may be opposite sides of the first portion of the semiconductor substrate. The access transistor has a first source/drain terminal electrically connected to a first source/drain terminal of the EEPROM transistor and the erase transistor has a first source/drain terminal electrically connected to a second source/drain terminal of the access transistor.

Abstract translation: 根据本发明的实施例的非易失性存储器件包括在半导体衬底的第一部分中的EEPROM晶体管，半导体衬底的第二部分中的存取晶体管和半导体衬底的第三部分中的擦除晶体管。 半导体衬底的第二部分在半导体衬底的第一部分的第一侧附近延伸，并且半导体衬底的第三部分相邻于半导体衬底的第一部分的第二侧延伸。 半导体衬底的第一部分的第一和第二侧可以是半导体衬底的第一部分的相对侧。 存取晶体管具有电连接到EEPROM晶体管的第一源极/漏极端子的第一源极/漏极端子，并且擦除晶体管具有电连接到存取晶体管的第二源极/漏极端子的第一源极/漏极端子。

公开(公告)号：US20140319701A1

公开(公告)日：2014-10-30

申请号：US14132516

申请日：2013-12-18

Applicant: Yong-hoon Kim ,  Hyo-soon Kang ,  Hee-seok Lee ,  Jang-ho Cho

Inventor： Yong-hoon Kim ,  Hyo-soon Kang ,  Hee-seok Lee ,  Jang-ho Cho

IPC: H01L25/18 ,  H01L23/50

CPC classification number: H01L25/18 ,  G11C5/025 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Abstract translation: 一种半导体芯片，包括衬底，布置在衬底上的第一数据焊盘和布置在衬底上的第一控制/寻址焊盘，其中第一数据焊盘布置在衬底的边缘区域中，并且第一控制/地址焊盘 布置在基板的中心区域中。

公开(公告)号：US08873245B2

公开(公告)日：2014-10-28

申请号：US13113239

申请日：2011-05-23

Applicant: Yong-hoon Kim ,  Hee-seok Lee

Inventor： Yong-hoon Kim ,  Hee-seok Lee

IPC: H05K1/18 ,  H01L25/10 ,  H01L25/065 ,  H05K3/34 ,  H05K3/28

CPC classification number: H05K1/183 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An embedded chip-on-chip package includes a printed circuit board having a recessed semiconductor chip mounting unit constituted by a recess in the printed circuit board and a circuit pattern at the bottom of the recess, a first semiconductor chip embedded in the recessed semiconductor chip mounting unit and electrically connected to the circuit pattern at the bottom of the recess, and a second semiconductor chip mounted to the recessed semiconductor chip mounting unit and electrically connected to the first semiconductor chip and the printed circuit board independently of each other.

Abstract translation: 嵌入式芯片芯片封装包括印刷电路板，其具有由印刷电路板中的凹部构成的凹陷半导体芯片安装单元和凹部底部的电路图案，嵌入在凹陷半导体芯片中的第一半导体芯片 安装单元，并且电连接到凹部的底部处的电路图案，以及安装到凹陷半导体芯片安装单元并且彼此独立地电连接到第一半导体芯片和印刷电路板的第二半导体芯片。

公开(公告)号：US08445996B2

公开(公告)日：2013-05-21

申请号：US12568224

申请日：2009-09-28

Applicant: Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

Inventor： Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

IPC: H01L23/60

CPC classification number: H01L23/552 ,  H01L23/60 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip.

Abstract translation: 半导体封装包括主衬底，具有第一侧和第二侧的半导体芯片，设置在主衬底上并与主衬底电连接的半导体芯片的第一侧和形成在主衬底的第二侧上的导电网络 半导体芯片。

公开(公告)号：US06576374B1

公开(公告)日：2003-06-10

申请号：US09605429

申请日：2000-06-29

Applicant: Yong-hoon Kim

Inventor： Yong-hoon Kim

IPC: G03F900

CPC classification number: G03F1/30 ,  G03F7/09

Abstract: A mask blank includes a transparent substrate, a light shield layer formed on the upper surface of the transparent substrate, and a multi-functional protective layer formed on the light shield layer. To make a phase shift mask from the blank, the protective layer is patterned, and the light shield layer is etched using the protective layer pattern as an etch mask. The phase shift region is formed by etching a groove in the second region of the substrate while the protective layer pattern protects the light shield layer. Therefore, undesirable residue is prevented from forming at the bottom of the groove constituting the phase shift region. The method also entails patterning a photosensitive layer on the protective layer, and patterning the protective layer by using the patterned photosensitve layer as a mask. In this case, the structure is cleaned so that no residue remains on the exposed portions of the light shield layer.

Abstract translation: 掩模坯料包括透明基板，形成在透明基板的上表面上的遮光层和形成在遮光层上的多功能保护层。 为了从空白制作相移掩模，图案化保护层，并且使用保护层图案作为蚀刻掩模蚀刻遮光层。 通过在衬底的第二区域中蚀刻凹槽来形成相移区域，同时保护层图案保护遮光层。 因此，防止在构成相移区域的槽的底部形成不希望的残留物。 该方法还需要在保护层上图案化感光层，并且通过使用图案化感光层作为掩模来图案化保护层。 在这种情况下，清洁该结构，使得在遮光层的露出部分上不残留残留物。

公开(公告)号：US6081365A

公开(公告)日：2000-06-27

申请号：US287634

申请日：1999-04-07

Applicant: Yong-hoon Kim

Inventor： Yong-hoon Kim

IPC: G02F1/11 ,  G02F1/33

CPC classification number: G02F1/11 ,  G02F2201/38

Abstract: An acousto-optic modulator comprised of an acousto-optic element coated with an anti-reflection layer, and a method of manufacturing the same, are provided. The acousto-optic modulator includes an anti-reflection layer, comprised of at least two coating layers having different refractive indices, formed on the light incident/emitting surface of an ultrasonic medium for modulating a light beam incident from an optical source.

Abstract translation: 提供了由涂覆有抗反射层的声光元件组成的声光调制器及其制造方法。 该声光调制器包括一个抗反射层，该反射层由至少两层具有不同折射率的涂层形成在超声介质的光入射/发射表面上，用于调制从光源入射的光束。