公开(公告)号：US20100013066A1

公开(公告)日：2010-01-21

申请号：US12568224

申请日：2009-09-28

申请人： Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

发明人： Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

IPC分类号： H01L23/60 ,  H01L23/52

CPC分类号： H01L23/552 ,  H01L23/60 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip.

摘要翻译： 半导体封装包括主衬底，具有第一侧和第二侧的半导体芯片，设置在主衬底上并与主衬底电连接的半导体芯片的第一侧和形成在主衬底的第二侧上的导电网络 半导体芯片。

公开(公告)号：US08445996B2

公开(公告)日：2013-05-21

申请号：US12568224

申请日：2009-09-28

申请人： Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

发明人： Yong-hoon Kim ,  Hee-seok Lee ,  Yun-seok Choi

IPC分类号： H01L23/60

CPC分类号： H01L23/552 ,  H01L23/60 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip.

摘要翻译： 半导体封装包括主衬底，具有第一侧和第二侧的半导体芯片，设置在主衬底上并与主衬底电连接的半导体芯片的第一侧和形成在主衬底的第二侧上的导电网络 半导体芯片。

公开(公告)号：US07508680B2

公开(公告)日：2009-03-24

申请号：US11779324

申请日：2007-07-18

申请人： Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song ,  Young-sang Cho ,  Na-rae Shin

发明人： Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song ,  Young-sang Cho ,  Na-rae Shin

IPC分类号： H05K1/16 ,  H01F27/28 ,  H01L23/48

CPC分类号： H01F21/12 ,  H01F41/045 ,  H05K1/147 ,  H05K1/165

摘要： An adjustable-inductance (AI) filter, a tape distribution substrate including the filter, and a display panel assembly including the tape distribution substrate are provided. The adjustable-inductance (AI) filter includes a filter distribution line including first and second end portions each having a first line width, at least one repair pattern having a second line width and disposed between the first and second end portions, and at least one unit filter bank connected in parallel to the at least one repair pattern, respectively.

摘要翻译： 提供可调电感（AI）滤波器，包括滤波器的带分配基板以及包括带分布基板的显示面板组件。 可调电感（AI）滤波器包括滤波器分配线，滤波器分配线包括每个具有第一线宽度的第一和第二端部，具有第二线宽并且设置在第一和第二端部之间的至少一个修复图案，以及至少一个 单元滤波器组分别与所述至少一个修复模式并联连接。

公开(公告)号：US07705433B2

公开(公告)日：2010-04-27

申请号：US11870533

申请日：2007-10-11

申请人： Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song

发明人： Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package includes a chip including a conductive pattern thereon, a conductive network attached on a surface of the chip to absorb static electricity, at least one conductive rod attached to the conductive network, wherein the at least one conductive rod is formed substantially perpendicularly to the conductive network, and a grounding portion discharging the static electricity absorbed from the conductive network.

摘要翻译： 半导体封装包括其上包括导电图案的芯片，附接在芯片的表面上以吸收静电的导电网络，附接到导电网络的至少一个导电棒，其中至少一个导电棒基本上垂直于 导电网络，以及放电从导电网吸收的静电的接地部分。

公开(公告)号：US20080087988A1

公开(公告)日：2008-04-17

申请号：US11870533

申请日：2007-10-11

申请人： Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song

发明人： Hee-seok Lee ,  Yun-seok Choi ,  Eun-seok Song

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package includes a chip including a conductive pattern thereon, a conductive network attached on a surface of the chip to absorb static electricity, at least one conductive rod attached to the conductive network, wherein the at least one conductive rod is formed substantially perpendicularly to the conductive network, and a grounding portion discharging the static electricity absorbed from the conductive network.

摘要翻译： 半导体封装包括其上包括导电图案的芯片，附接在芯片的表面上以吸收静电的导电网络，附接到导电网络的至少一个导电棒，其中至少一个导电棒基本上垂直于 导电网络，以及放电从导电网吸收的静电的接地部分。

公开(公告)号：US20130001797A1

公开(公告)日：2013-01-03

申请号：US13531289

申请日：2012-06-22

申请人： Yun-seok Choi ,  Hee-seok Lee ,  Tae-je Cho

发明人： Yun-seok Choi ,  Hee-seok Lee ,  Tae-je Cho

IPC分类号： H01L23/498

CPC分类号： H01L25/105 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331

摘要： A package on package (PoP) employing a through substrate via (TSV) technique in order to reduce the size of a semiconductor chip, has vertically narrow pitches, and forms a higher number of connection terminals. The PoP include a first substrate with a recess disposed in a first surface of the substrate, and a semiconductor chip disposed at the recess. The PoP also includes a semiconductor package connected to the first semiconductor package. The first substrate includes TSVs for electronically connecting the semiconductor package and the semiconductor chip, and routing lines for re-distributing the signals/and or power transmitted via the TSVs.

摘要翻译： 为了减小半导体芯片的尺寸，采用直通衬底通孔（TSV）技术的封装（PoP）具有垂直窄的间距，并且形成更多数量的连接端子。 PoP包括具有设置在基板的第一表面中的凹部的第一基板和设置在凹部处的半导体芯片。 PoP还包括连接到第一半导体封装的半导体封装。 第一衬底包括用于电连接半导体封装和半导体芯片的TSV以及用于重新分配通过TSV传输的信号和/或功率的路由线。

公开(公告)号：US08106425B2

公开(公告)日：2012-01-31

申请号：US11819628

申请日：2007-06-28

申请人： Yun-seok Choi ,  Na-rae Shin ,  Hee-seok Lee

发明人： Yun-seok Choi ,  Na-rae Shin ,  Hee-seok Lee

IPC分类号： H01L23/52

CPC分类号： H05K1/165 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0233 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/09263 ,  H01L2924/00

摘要： Example embodiments relate to an interconnection substrate and a semiconductor chip package and a display system including the same. The interconnection substrate may include a base film, a signal line provided on the base film, a power line provided on the base film as a line pattern including a plurality of bent portions, and a ground line provided on the base film in parallel with the power line. The interconnection substrate may further include a semiconductor chip provided on the base film, wherein the power, ground, and/or signal lines are electrically connected to the semiconductor chip to form a semiconductor chip package. A display system may include the above semiconductor chip package, a screen displaying an image, and a PCB generating a signal. The semiconductor chip may be connected between the PCB and the screen and relay the generated signal from the PCB to the screen. Use of the power, ground, and/or signal lines having a plurality of bent portions may reduce electromagnetic interference (EMI) within the display system.

摘要翻译： 示例性实施例涉及互连衬底和半导体芯片封装以及包括其的显示系统。 互连基板可以包括基膜，设置在基膜上的信号线，设置在基膜上的电源线作为包括多个弯曲部的线图案，以及设置在基膜上的与线平行的接地线 电源线。 互连基板还可以包括设置在基膜上的半导体芯片，其中电源，接地和/或信号线电连接到半导体芯片以形成半导体芯片封装。 显示系统可以包括上述半导体芯片封装，显示图像的屏幕和产生信号的PCB。 半导体芯片可以连接在PCB和屏幕之间，并将产生的信号从PCB继电器传递到屏幕。 使用具有多个弯曲部分的电源，接地和/或信号线可以减少显示系统内的电磁干扰（EMI）。

公开(公告)号：US20080023844A1

公开(公告)日：2008-01-31

申请号：US11819628

申请日：2007-06-28

申请人： Yun-seok Choi ,  Na-rae Shin ,  Hee-seok Lee

发明人： Yun-seok Choi ,  Na-rae Shin ,  Hee-seok Lee

IPC分类号： H01L23/52

CPC分类号： H05K1/165 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0233 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/09263 ,  H01L2924/00

摘要： Example embodiments relate to an interconnection substrate and a semiconductor chip package and a display system including the same. The interconnection substrate may include a base film, a signal line provided on the base film, a power line provided on the base film as a line pattern including a plurality of bent portions, and a ground line provided on the base film in parallel with the power line. The interconnection substrate may further include a semiconductor chip provided on the base film, wherein the power, ground, and/or signal lines are electrically connected to the semiconductor chip to form a semiconductor chip package. A display system may include the above semiconductor chip package, a screen displaying an image, and a PCB generating a signal. The semiconductor chip may be connected between the PCB and the screen and relay the generated signal from the PCB to the screen. Use of the power, ground, and/or signal lines having a plurality of bent portions may reduce electromagnetic interference (EMI) within the display system.

摘要翻译： 示例性实施例涉及互连衬底和半导体芯片封装以及包括其的显示系统。 互连基板可以包括基膜，设置在基膜上的信号线，设置在基膜上的电源线作为包括多个弯曲部的线图案，以及设置在基膜上的与线平行的接地线 电源线。 互连基板还可以包括设置在基膜上的半导体芯片，其中电源，接地和/或信号线电连接到半导体芯片以形成半导体芯片封装。 显示系统可以包括上述半导体芯片封装，显示图像的屏幕和产生信号的PCB。 半导体芯片可以连接在PCB和屏幕之间，并将产生的信号从PCB继电器传递到屏幕。 使用具有多个弯曲部分的电源，接地和/或信号线可以减少显示系统内的电磁干扰（EMI）。

公开(公告)号：US09059067B2

公开(公告)日：2015-06-16

申请号：US13235546

申请日：2011-09-19

申请人： Yun-seok Choi ,  So-young Lim ,  In-won O

发明人： Yun-seok Choi ,  So-young Lim ,  In-won O

IPC分类号： H01L29/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/147 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/0401

摘要： A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip.

摘要翻译： 半导体器件包括安装半导体芯片的插入器。 插入器包括硅基板，其具有形成在第一表面上的凹陷区域，穿过硅基板的第一区域的第一通孔从第一表面到相对的第二表面，设置在凹陷区域中的绝缘体和第一引线 至少部分地设置在所述绝缘体上并将所述第一通孔电连接到所述半导体芯片。

公开(公告)号：US20110304364A1

公开(公告)日：2011-12-15

申请号：US13083931

申请日：2011-04-11

申请人： Jae-wook Yoo ,  Kyoung-sel Choi ,  Yun-seok Choi

发明人： Jae-wook Yoo ,  Kyoung-sel Choi ,  Yun-seok Choi

IPC分类号： H03L7/08 ,  H05K9/00 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/15311 ,  H03L7/18 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Provided is an electromagnetic interference (EMI) removing device for active reduction of electromagnetic interference and a semiconductor package including the same. The EMI removing device may include a film substrate having an antenna pattern configured to generate a second electromagnetic wave, which may have substantially the same frequency band, modulation mode, and directivity as a first electromagnetic wave generated by a first semiconductor chip and a phase opposite to a phase of the first electromagnetic wave

摘要翻译： 提供了用于主动地减少电磁干扰的电磁干扰（EMI）去除装置和包括其的半导体封装。 EMI去除装置可以包括具有被配置为产生第二电磁波的天线图案的薄膜基板，该第二电磁波可以具有与由第一半导体芯片产生的第一电磁波和相位相反的基本上相同的频带，调制模式和方向性 到第一电磁波的相位