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    Method for determining and recovering from loss of synchronization, Communication Units and Integrated Circuits therefor
    12.
    发明申请
    Method for determining and recovering from loss of synchronization, Communication Units and Integrated Circuits therefor 有权
    用于确定和恢复同步丢失的方法，通信单元和集成电路

    公开(公告)号：US20170078996A1

    公开(公告)日：2017-03-16

    申请号：US14851078

    申请日：2015-09-11

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Igor Shoihet ,  Ofer Lent ,  Roy M Shor

    IPC: H04W56/00 ,  H04W4/06 ,  H04W76/06

    CPC classification number: H04W56/0015 ,  H04W4/06 ,  H04W56/003 ,  H04W76/36

    Abstract: A method of recovery from a time-synchronization loss in a communication unit between a first processor supporting physical layer communications and a second processor supporting layer-2 communications is described. The method comprises: detecting, by the first processor, that a loss of sync has occurred between the first and second processors; in response to said detecting, stopping sending subsequent physical layer messages from the first processor to the second processor, for example to allow the second processor to consume any old pending messages; re-starting a messaging process by the first processor by sending at least one new message to the second processor with updated System Frame Number, SFN, and Sub-Frame, SF, counter value; and receiving at the first processor at least one subsequent response message from the second processor acknowledging receipt of at least one new message with an indication of the received and updated SFN and SF counter value of that message thereby confirming synchronization being restored.

    Abstract translation: 描述了从支持物理层通信的第一处理器和支持第二层通信的第二处理器之间的通信单元中的时间同步损失中恢复的方法。 该方法包括：由第一处理器检测在第一和第二处理器之间发生同步丢失; 响应于所述检测，停止将后续物理层消息从第一处理器发送到第二处理器，例如允许第二处理器消耗任何旧的待处理消息; 通过用更新的系统帧号，SFN和子帧，SF，计数器值向第二处理器发送至少一个新消息，由第一处理器重新启动消息处理; 以及在所述第一处理器处接收来自所述第二处理器的至少一个后续响应消息，所述至少一个后续响应消息确认接收到所述至少一个新消息，并具有所述消息的接收和更新的SFN和SF计数器值的指示，从而确认恢复同步。

    Configurable cell design using capacitive coupling for enhanced timing closure
    13.
    发明授权
    Configurable cell design using capacitive coupling for enhanced timing closure 有权
    使用电容耦合的可配置单元设计可增强时序闭合

    公开(公告)号：US09576101B2

    公开(公告)日：2017-02-21

    申请号：US14635827

    申请日：2015-03-02

    Applicant: Vijay Bhargava ,  Naveen Kumar ,  Kushagra Khorwal

    Inventor： Vijay Bhargava ,  Naveen Kumar ,  Kushagra Khorwal

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/62

    Abstract: A method for achieving clock timing closure in an integrated circuit (IC) design includes designing an IC using one or more component cells selected from a cell library to produce the design. A timing analysis of the design is performed to determine if timing constraints are satisfied. When a given time constraint is not satisfied, a component cell selected from the cell library is replaced with a replacement cell that has the same function and the same footprint as the replaced component cell, but has a different timing characteristic based on the phase relationship of the signal being capacitively coupled to enhance the likelihood of meeting the given time constraint. The timing analysis is repeated with the replacement cell. The process of replacing component cells and performing timing analysis may be iterative.

    Abstract translation: 用于在集成电路（IC）设计中实现时钟定时闭合的方法包括使用从单元库选择的一个或多个组件单元来设计IC以产生设计。 执行设计的定时分析以确定是否满足时序约束。 当不满足给定的时间约束时，从具有与被替代的分量单元相同的功能和相同的占空比的替换单元替换从单元库中选择的分量单元，但是具有基于相位关系的不同的定时特性 信号被电容耦合以增强满足给定时间约束的可能性。 用替换单元重复时序分析。 更换组件单元和执行时序分析的过程可能是迭代的。

    PHASE LOCKED LOOP CIRCUIT, INTEGRATED CIRCUIT, COMMUNICATION UNIT AND METHOD THEREFOR
    14.
    发明申请
    PHASE LOCKED LOOP CIRCUIT, INTEGRATED CIRCUIT, COMMUNICATION UNIT AND METHOD THEREFOR 有权
    相位锁定环路，集成电路，通信单元及其方法

    公开(公告)号：US20170047933A1

    公开(公告)日：2017-02-16

    申请号：US14994197

    申请日：2016-01-13

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Pierre SAVARY ,  Birama GOUMBALLA ,  Didier SALLE

    IPC: H03L7/099 ,  H03L7/085 ,  H03L7/08

    CPC classification number: H03L7/085

    Abstract: A phase locked loop circuit includes a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage; a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage; a loop filter having an input and an output; and a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO.

    Abstract translation: 锁相环电路包括被配置为接收振荡器调谐电压的压控振荡器VCO; 相位检测器，被配置为接收输入信号和参考信号，并产生根据振荡器调谐电压而变化的相位差脉冲信号; 具有输入和输出的环路滤波器; 以及电平移位器电路，耦合到相位检测器和环路滤波器输入的输出端，并被配置为向相位差脉冲信号施加电平移位，使得电平移位被配置为补偿VCO增益，并且环路滤波器平均相位差 脉冲信号以将平均信号输出到VCO。

    ESD PROTECTION STRUCTURE
    15.
    发明申请
    ESD PROTECTION STRUCTURE 有权
    ESD保护结构

    公开(公告)号：US20170005081A1

    公开(公告)日：2017-01-05

    申请号：US14953711

    申请日：2015-11-30

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Jean Philippe LAINE ,  Patrice BESSE

    IPC: H01L27/02 ,  H01L29/74 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L27/0255 ,  H01L27/0262 ,  H01L29/0653 ,  H01L29/66371 ,  H01L29/7416

    Abstract: An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, a first N-doped section comprising a deep N-well structure, a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well. The ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure and forming a part of the second P-doped section of the thyristor structure.

    Abstract translation: 包括晶闸管结构的ESD保护结构。 晶闸管结构由第一P掺杂部分形成，第一P掺杂部分包括形成在P掺杂外延层的第一区域内的第一P掺杂阱，包含深N阱结构的第一N掺杂部分， 掺杂部分，其包括形成在所述外延层的第二区域内的第二P掺杂阱，以及第二N掺杂部分，其包括形成在所述第二P掺杂阱的表面内的N掺杂接触区域。 ESD保护结构还包括形成在深N阱结构的上表面上并形成晶闸管结构的第二P掺杂部分的一部分的P掺杂区域。

    Temperature sensor circuitry with scaled voltage signal
    16.
    发明授权
    Temperature sensor circuitry with scaled voltage signal 有权
    具有缩放电压信号的温度传感器电路

    公开(公告)号：US09528883B2

    公开(公告)日：2016-12-27

    申请号：US14258629

    申请日：2014-04-22

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Ravindraraj Ramaraju ,  David R. Bearden ,  Sunitha Manickavasakam ,  Venkataram M. Mooraka ,  Hector Sanchez

    IPC: G01K7/01 ,  G05F3/30

    CPC classification number: G01K7/01 ,  G05F3/30

    Abstract: Temperature sensing circuitry implemented on a semiconductor integrated circuit that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensing circuitry converts a voltage signal that is proportional to the temperature to a frequency-based signal, which is converted to a digital bit value. A scalar factor is applied to another voltage signal that is inversely proportional to the temperature to produce a scaled voltage signal. The scaled voltage signal is converted to a second frequency-based signal, which is converted to a digital bit value, and then the two digital bit values are compared. The temperature is determined when the digital bit values substantially match.

    Abstract translation: 在半导体集成电路上实现的温度感测电路，其感测位置处的温度，数字化感测的温度，然后输出表示这种感测温度的信号。 温度感测电路将与温度成比例的电压信号转换为基于频率的信号，其被转换为数字位值。 将标量因子应用于与温度成反比的另一个电压信号，以产生缩放的电压信号。 经缩放的电压信号被转换为第二基于频率的信号，其被转换为数字位值，然后比较两个数字位值。 当数字位值基本匹配时确定温度。

    Apparatus and method for memory copy at a processor
    17.
    发明授权
    Apparatus and method for memory copy at a processor 有权
    在处理器处进行存储器复制的装置和方法

    公开(公告)号：US09524162B2

    公开(公告)日：2016-12-20

    申请号：US13455800

    申请日：2012-04-25

    Applicant: Thang M. Tran ,  James Yang

    Inventor： Thang M. Tran ,  James Yang

    IPC: G06F12/00 ,  G06F9/30 ,  G06F12/08 ,  G06F9/38

    CPC classification number: G06F9/30032 ,  G06F9/30043 ,  G06F9/3838 ,  G06F9/384 ,  G06F12/0897

    Abstract: A processor uses a dedicated buffer to reduce the amount of time needed to execute memory copy operations. For each load instruction associated with the memory copy operation, the processor copies the load data from memory to the dedicated buffer. For each store operation associated with the memory copy operation, the processor retrieves the store data from the dedicated buffer and transfers it to memory. The dedicated buffer is separate from a register file and caches of the processor, so that each load operation associated with a memory copy operation does not have to wait for data to be loaded from memory to the register file. Similarly, each store operation associated with a memory copy operation does not have to wait for data to be transferred from the register file to memory.

    Abstract translation: 处理器使用专用缓冲器来减少执行内存复制操作所需的时间。 对于与存储器复制操作相关联的每个加载指令，处理器将负载数据从存储器复制到专用缓冲区。 对于与存储器复制操作相关联的每个存储操作，处理器从专用缓冲器检索存储数据并将其传送到存储器。 专用缓冲器与寄存器文件和处理器的高速缓存分开，使得与存储器复制操作相关联的每个加载操作不必等待数据从存储器加载到寄存器文件。 类似地，与存储器复制操作相关联的每个存储操作不必等待数据从寄存器文件传送到存储器。

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