公开(公告)号：US09136280B2

公开(公告)日：2015-09-15

申请号：US14328818

申请日：2014-07-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: H01L27/12 ,  G11C16/04 ,  G11C11/403 ,  H01L27/115

CPC classification number: H01L27/1214 ,  G11C11/403 ,  G11C16/0425 ,  G11C16/0433 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.

Abstract translation: 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态下具有小的漏电流，读取晶体管包括与写入晶体管不同的半导体材料， 和电容器。 通过接通写入晶体管并将数据写入或重写到存储器单元中，并将电位施加到写入晶体管的源极和漏极，电容器的一个电极和读取的晶体管的栅电极之一的节点 彼此电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。

公开(公告)号：US20150131367A1

公开(公告)日：2015-05-14

申请号：US14539067

申请日：2014-11-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato

IPC: G11C11/417 ,  G11C5/14

CPC classification number: G11C5/147 ,  G11C11/404 ,  G11C11/4074 ,  G11C14/0054

Abstract: A normally-off state of an OS transistor is maintained or an on-state current thereof is increased without additionally generating a positive potential or a negative potential. When data is written to a node connecting an OS transistor and a capacitor, a potential supplied to the other side of the capacitor is set to an L level, and when the data is retained, the potential is switched from the L level to an H level. In addition, a power switch for a volatile memory circuit is provided on a low power supply potential side so that the supply of a power supply voltage can be stopped. Accordingly, at the time of data retention, a source and a drain of the OS transistor can be set at a high potential, whereby the normally-off state can be maintained and the on-state current can be increased.

Abstract translation: 维持OS晶体管的常关状态或者不增加正电位或负电位而增加导通状态电流。 当将数据写入连接OS晶体管和电容器的节点时，提供给电容器另一侧的电位被设置为L电平，并且当保持数据时，电位从L电平切换到H 水平。 此外，用于易失性存储器电路的电源开关设置在低电源电位侧，使得可以停止供电电压。 因此，在数据保持时，OS晶体管的源极和漏极可以被设置为高电位，由此可以保持常关状态并且可以增加导通电流。

公开(公告)号：US20150070962A1

公开(公告)日：2015-03-12

申请号：US14479707

申请日：2014-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Kiyoshi Kato

IPC: G11C5/14 ,  G11C5/06

CPC classification number: G11C5/14 ,  G11C11/403 ,  H01L27/1225 ,  H01L27/1255

Abstract: To provide a memory device with short overhead time and a semiconductor device including the memory device. A memory device includes a first circuit that can retain data and a second circuit by the supply of power supply voltage. The second circuit includes a third circuit that selects a first potential corresponding to the data or a second potential supplied to a first wiring; a first transistor having a channel formation region in an oxide semiconductor film; a capacitor that hold the first potential or the second potential that is selected by the third circuit and supplied through the first transistor; and a second transistor controlling a conduction state between the first circuit and a second wiring that can supply a third potential in accordance with the potential retained in the capacitor.

Abstract translation: 提供具有较短开销时间的存储器件和包括存储器件的半导体器件。 存储器件包括通过提供电源电压可以保留数据的第一电路和第二电路。 第二电路包括第三电路，其选择对应于数据的第一电位或提供给第一布线的第二电位; 在氧化物半导体膜中具有沟道形成区域的第一晶体管; 保持由第三电路选择并通过第一晶体管提供的第一电位或第二电位的电容器; 以及第二晶体管，其控制所述第一电路和第二布线之间的导通状态，所述第二布线可以根据保持在所述电容器中的电位提供第三电位。

公开(公告)号：US08902640B2

公开(公告)日：2014-12-02

申请号：US13861681

申请日：2013-04-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/24 ,  H01L27/12 ,  H01L27/115 ,  G11C11/405 ,  H01L27/108 ,  G11C16/04

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract translation: 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

公开(公告)号：US08892158B2

公开(公告)日：2014-11-18

申请号：US13916666

申请日：2013-06-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H04B1/28 ,  H04M1/00 ,  H04B7/00 ,  H01L27/06 ,  H01L29/786 ,  H04B1/40 ,  H01L27/12

CPC classification number: H01L29/78696 ,  G06K19/07749 ,  G06K19/07773 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H01L2223/6677 ,  H04B1/40 ,  Y02D70/00

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

Abstract translation: 目的是实现具有无线通信功能的半导体器件的低功耗和长寿命。 可以通过使用氧化物半导体形成沟道形成区域的晶体管将用作电源和特定电路的电池彼此电连接的方式实现目的。 氧化物半导体的氢浓度低于或等于5×1019（原子/ cm3）。 因此，可以减小晶体管的漏电流。 结果，可以降低处于待机状态的半导体器件的功耗。 此外，半导体器件可以具有长的寿命。

公开(公告)号：US08854084B2

公开(公告)日：2014-10-07

申请号：US14048099

申请日：2013-10-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Shionoiri ,  Kiyoshi Kato ,  Munehiro Azami

IPC: G01R19/00 ,  G11C11/4091 ,  H03F3/45 ,  G11C7/06 ,  G11C11/413

CPC classification number: H03F3/45179 ,  G01R19/00 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/413 ,  G11C2207/063 ,  H03F3/45183 ,  H03F3/45188 ,  H03F2203/45396 ,  H03F2203/45506 ,  H03F2203/45546 ,  H03F2203/45551 ,  H03F2203/45702 ,  H03F2203/45726

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract translation: 根据本发明的用于检测输入到第一输入端和第二输入端的信号的电位差的读出放大器包括：第一装置，用于将对应于第一和第二晶体管的阈值电压的电压施加到栅极源电压 第一和第二晶体管，以及用于将输入到第一和第二输入端的信号传送到第一和第二晶体管的栅极的第二装置。 在这种情况下，校正第一和第二晶体管的阈值变化。

公开(公告)号：US20140293711A1

公开(公告)日：2014-10-02

申请号：US14223071

申请日：2014-03-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Takuro Ohmaru ,  Yasuyuki Takahashi

IPC: G11C7/12

CPC classification number: G11C11/4091 ,  G11C11/401 ,  G11C11/4074

Abstract: The first circuit has a function of retaining data in a first period during which a power supply voltage is supplied. The second circuit has functions of saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which application of the power supply voltage is stopped. The third circuit has functions of saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which application of the power supply voltage is stopped. The second circuit is capable of being written with the data for a shorter time than the third circuit. The third circuit is capable of maintaining the data for a longer time than the second circuit.

Abstract translation: 第一电路具有在提供电源电压的第一时段中保持数据的功能。 第二电路具有在第一时间段内保存保留在第一电路中的数据的功能，并且在停止施加电源电压的第二周期中保持从第一电路保存的数据。 第三电路具有在第二时段中保存保留在第二电路中的数据的功能，并且在停止施加电源电压的第三周期中保留从第二电路保存的数据。 第二电路能够以比第三电路更短的时间写入数据。 第三电路能够保持数据比第二电路更长的时间。

公开(公告)号：US20140284600A1

公开(公告)日：2014-09-25

申请号：US14297692

申请日：2014-06-06

Applicant: Semiconductor Energy Laboratory Co., Ltd

Inventor： Kiyoshi Kato

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/124 ,  G06F1/32 ,  G06F7/5016 ,  G06F2207/3872 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Abstract translation: 为了降低功耗，具有基于输入信号进行逻辑运算处理的功能的运算电路，将根据逻辑运算处理结果存储的电位存储为存储数据，并输出具有值的信号 对应于存储的数据作为输出信号。 算术电路包括执行逻辑运算处理的运算部，控制是否设定了与逻辑运算处理结果对应的电位的第一电位的第一场效应晶体管，以及控制是否 输出信号数据的电位被设定为作为参考电位的第二电位。

公开(公告)号：US20140204696A1

公开(公告)日：2014-07-24

申请号：US14160800

申请日：2014-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Takuro Ohmaru ,  Yasuyuki Takahashi

IPC: G11C5/14

CPC classification number: G11C11/22 ,  G11C11/24

Abstract: Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied. The third circuit includes a transistor in which a channel formation region is provided in an oxide semiconductor film and a capacitor to which a potential corresponding to the data is supplied through the transistor.

Abstract translation: 提供了具有降低的架空功率的存储器件。 一种存储装置，包括：第一电路，在供给电源电压的第一期间保持数据; 第二电路在第一时段中保存保留在第一电路中的数据，并且在不提供电源电压的第二周期内保留从第一电路保存的数据; 以及第三电路，在第二时段中保存保留在第二电路中的数据，并且在不提供电源电压的第三周期内保持从第二电路保存的数据。 第三电路包括其中沟道形成区域设置在氧化物半导体膜中的晶体管和通过晶体管提供对应于数据的电位的电容器。

公开(公告)号：US20140169072A1

公开(公告)日：2014-06-19

申请号：US14183644

申请日：2014-02-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: G11C7/12 ,  G11C11/24

CPC classification number: G11C7/12 ,  G11C11/24 ,  G11C11/405 ,  G11C2211/4016 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225

Abstract: An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

Abstract translation: 目的在于提供一种具有新颖结构的半导体器件。 第一个接线 第二布线 第三布线，第四布线; 第一晶体管，包括第一栅极电极，第一源极电极和第一漏极电极; 包括第二晶体管，包括第二栅电极，第二源电极和第二漏电极。 第一晶体管设置在包括半导体材料的衬底上，并且第二晶体管包括氧化物半导体层。