公开(公告)号：US20250046353A1

公开(公告)日：2025-02-06

申请号：US18927574

申请日：2024-10-25

Applicant: Micron Technology, Inc.

Inventor： Erik V. Pohlmann

IPC: G11C7/10 ,  G11C8/18

Abstract: Methods, systems, and devices for dynamic random access memory speed bin compatibility are described. For instance, a device (e.g., a memory device, a host device) may combine a first parameter with a second parameter to generate a third parameter, where the first parameter may be associated with a duration for a clock that is coupled with a memory array to perform a clock cycle and the second parameter may be associated with a timing constraint associated with initiating an access operation for the memory array. The device may determine a latency of a column address strobe based on the third parameter relative to (e.g., satisfying) a threshold value and may access one or more memory cells of the memory array based on the latency of the column address strobe.

公开(公告)号：US20250045156A1

公开(公告)日：2025-02-06

申请号：US18774652

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Fan Zhou

IPC: G06F11/10

Abstract: A decoding operation is performed by receiving a command to read a correction matrix comprising multiple bit-values from memory of a decoder. The decoding operation also includes, responsive to receipt of the command, generating, using circuitry of a decoder, a predetermined correction matrix comprising a same bit-value. The decoding operation further includes providing the predetermined correction matrix to a decision engine to perform the decoding operation.

公开(公告)号：US20250045153A1

公开(公告)日：2025-02-06

申请号：US18786254

申请日：2024-07-26

Applicant: Micron Technology, Inc.

Inventor： Joseph M. McCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

Abstract: Provided herein is a memory system including logical to physical memory address translation logic to build up a minimum address space containing a memory device address with defects, the translation being based on memory correction attempts. For each correction attempt, the logical address is first translated to a memory device physical address and bit positions at the physical address are compared with an existing error bit pattern to determine if marking should be applied to the memory device. If the bit positions do not match the existing error bit pattern, but errors are corrected from the marked memory device, the existing error bit pattern will be updated to reflect a new error bit pattern.

公开(公告)号：US12219765B2

公开(公告)日：2025-02-04

申请号：US18209173

申请日：2023-06-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/06 ,  G11C13/00 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/50 ,  H10B63/00 ,  H10N70/20

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US12218681B2

公开(公告)日：2025-02-04

申请号：US17949635

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Eyal En Gad

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/15

Abstract: A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

公开(公告)号：US12218119B2

公开(公告)日：2025-02-04

申请号：US17931284

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/16

Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

公开(公告)号：US12217824B2

公开(公告)日：2025-02-04

申请号：US18160292

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Amitava Majumdar ,  Cagdas Dirik ,  Sujeet Ayyapureddi ,  Yang Lu ,  Ameen D. Akel ,  Danilo Caraccio ,  Niccolo′ Izzo ,  Elliott C. Cooper-Balis ,  Markus H. Geiger

IPC: G11C29/52 ,  G11C7/22 ,  G11C7/24

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

公开(公告)号：US12217801B2

公开(公告)日：2025-02-04

申请号：US18076537

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30

Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

公开(公告)号：US12217799B2

公开(公告)日：2025-02-04

申请号：US18119997

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

公开(公告)号：US12216573B2

公开(公告)日：2025-02-04

申请号：US18395363

申请日：2023-12-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0891 ,  G11C11/56

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.