公开(公告)号：US09799776B2

公开(公告)日：2017-10-24

申请号：US14739634

申请日：2015-06-15

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US09793396B2

公开(公告)日：2017-10-17

申请号：US15169495

申请日：2016-05-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing Liu ,  Thomas Skotnicki

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

公开(公告)号：US20170288040A1

公开(公告)日：2017-10-05

申请号：US15088960

申请日：2016-04-01

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Emmanuel Augendre ,  Qing Liu ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/225 ,  H01L27/12 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/2257 ,  H01L21/3065 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785

Abstract: A method comprising: forming an SiGe layer on sidewalls of one or more fins of a semiconductor device by a non-selective deposition of amorphous SiGe, the fins being formed of Si or SiGe; depositing a silicon oxide layer over the SiGe layer; and forming an SiGe channel formation region within each fin by performing Ge enrichment to diffuse Ge atoms from the SiGe layer into the one or more fins.

公开(公告)号：US20170154900A1

公开(公告)日：2017-06-01

申请号：US15432492

申请日：2017-02-14

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/84 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02694 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

公开(公告)号：US09634103B2

公开(公告)日：2017-04-25

申请号：US14782190

申请日：2013-04-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS INC

Inventor： Maud Vinet ,  Laurent Grenouillet ,  Qing Liu

IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L21/311 ,  H01L21/32 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/41783 ,  H01L21/31133 ,  H01L21/32 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/6656

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

公开(公告)号：US09601511B2

公开(公告)日：2017-03-21

申请号：US14771016

申请日：2013-02-28

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud Vinet ,  Kangguo Cheng ,  Bruce Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/223 ,  H01L21/265 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

公开(公告)号：US20170077270A1

公开(公告)日：2017-03-16

申请号：US15361935

申请日：2016-11-28

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract translation: 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。

公开(公告)号：US20170033284A1

公开(公告)日：2017-02-02

申请号：US15293998

申请日：2016-10-14

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars ism stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

Abstract translation: 存储单元包括衬底层，多个硅化半导体鳍片堆叠在衬底层上并彼此间隔开。 第一金属衬垫层堆叠在多个硅化半导体鳍片上和衬底层上。 在第一金属衬垫层上堆叠多个第一接触柱，与多个硅化半导体鳍片中的不同的一个相邻。 可配置的电阻结构覆盖层叠在基板层上的第一金属衬垫层的部分和堆叠在多个硅化半导体鳍片中的每一个上的第一金属衬垫层的部分。 金属填充层堆叠在可配置电阻结构上。 多个第二接触柱堆叠在金属填充层上，与多个相邻的相邻硅化物半导体散热片之间的空间相邻。

公开(公告)号：US09543304B2

公开(公告)日：2017-01-10

申请号：US14677404

申请日：2015-04-02

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L29/66 ,  H01L27/085 ,  H01L27/098 ,  H01L29/78 ,  H01L29/808 ,  H01L29/417 ,  H01L29/10 ,  H01L21/283

CPC classification number: H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract translation: 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。

公开(公告)号：US09515185B2

公开(公告)日：2016-12-06

申请号：US14588116

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Hong He ,  Bruce Doris

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L27/12

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Abstract translation: 结构稳定的绝缘体上的FinFET采用氮化硅衬垫以防止SiGe鳍底部的稳定化氧化。 氮化硅衬垫阻止氧气进入翅片的下角，以便制造高浓度SiGe翅片。 氮化硅衬垫即使其厚度小于约5nm也是有效的。 使用SiN衬垫为具有较高锗含量，在25-55％锗浓度范围内的翅片提供结构稳定性。