公开(公告)号：US09577036B1

公开(公告)日：2017-02-21

申请号：US14939310

申请日：2015-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/764 ,  H01L21/823431 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.

Abstract translation: 半导体器件包括在半导体衬底上的半导体器件和半导体鳍片，其中半导体鳍片具有在由两个单元共享的公共边界处的鳍片隔离结构。 翅片隔离结构具有从半导体鳍片的顶部延伸到半导体衬底上的停止层的气隙。 气隙将半导体翅片分成半导体翅片的两个部分。 翅片隔离结构包括覆盖气隙顶部的电介质盖层。

公开(公告)号：US09559205B2

公开(公告)日：2017-01-31

申请号：US14725118

申请日：2015-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的翅片结构和覆盖翅片结构的一部分的栅极堆叠。 栅堆叠包括功函数层和栅介质层。 半导体器件结构还包括位于半导体衬底上并与栅堆叠相邻的隔离元件。 隔离元件与功函数层和栅极电介质层直接接触，并且隔离元件的较低宽度大于隔离元件的上部宽度。

公开(公告)号：US09536964B2

公开(公告)日：2017-01-03

申请号：US14725002

申请日：2015-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yin Shiao ,  Che-Cheng Chang ,  Tai-Shin Cheng ,  Wei-Ting Chen

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L23/485 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer. The method includes forming an antireflection layer over the dielectric layer, forming a hard mask layer over the antireflection layer and forming a patterned photoresist layer over the hard mask layer. The method includes etching a portion of the antireflection layer by performing a first etching process and etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process. The method includes etching through the dielectric layer by performing a third etching process to form a via portion on the first metal layer. The via portion includes a first sidewall and a second sidewall, and the slope of the first sidewall is different from that of the second sidewall.

Abstract translation: 提供了一种形成半导体器件结构的方法。 该方法包括在衬底上形成第一金属层，并在第一金属层上形成电介质层。 该方法包括在电介质层上形成抗反射层，在抗反射层上形成硬掩模层，并在硬掩模层上形成图案化的光致抗蚀剂层。 该方法包括通过执行第一蚀刻工艺和蚀刻穿过抗反射层并通过执行第二蚀刻工艺蚀刻介电层的一部分来蚀刻抗反射层的一部分。 该方法包括通过执行第三蚀刻工艺来蚀刻通过介电层，以在第一金属层上形成通孔部分。 通孔部分包括第一侧壁和第二侧壁，并且第一侧壁的斜面与第二侧壁的斜面不同。

公开(公告)号：US09502567B2

公开(公告)日：2016-11-22

申请号：US14621805

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

Abstract translation: 提供半导体结构及其形成方法。 该半导体结构包括在基板上形成的基板和翅片结构。 半导体结构还包括形成在翅片结构周围的隔离结构和横跨翅片结构形成的栅极结构。 此外，栅极结构包括形成在鳍状结构上的第一部分和形成在隔离结构上的第二部分，并且栅极结构的第二部分包括延伸到隔离结构中的延伸部分。

公开(公告)号：US09461043B1

公开(公告)日：2016-10-04

申请号：US14754627

申请日：2015-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Ting Chen

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

Abstract translation: 半导体器件包括衬底，第一栅极，第二栅极和绝缘结构。 基板包括第一翅片和第二翅片。 第一个门被放置在第一个鳍上。 第二个门设置在第二个翅片上。 在第一栅极和第二栅极之间形成间隙，并且间隙朝向衬底变宽。 绝缘结构设置在间隙中。 绝缘结构具有彼此相对的顶表面和底表面。 底面朝向基板。 面向第一门的顶面的边​​缘在顶面向内弯曲。

公开(公告)号：US09406680B1

公开(公告)日：2016-08-02

申请号：US14698831

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/306 ,  H01L29/161 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat portion.

Abstract translation: 半导体器件包括Fin FET晶体管。 鳍FET晶体管包括沿第一方向延伸的第一鳍结构，栅极堆叠以及源极和漏极。 栅堆叠包括栅极电极层和栅极电介质层，覆盖翅片结构的一部分并且沿垂直于第一方向的第二方向延伸。 源极和漏极中的每一个包括设置在鳍结构上的应力层。 应力层对栅叠层下的鳍结构的沟道层施加应力。 应力层穿过栅极叠层。 在垂直于第一和第二方向的第三方向上的应力层和翅片结构之间的垂直界面包括平坦部分。

公开(公告)号：US09331074B1

公开(公告)日：2016-05-03

申请号：US14611159

申请日：2015-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/70 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device includes first and second Fin FET transistors and a separation plug made of an insulating material and disposed between the first and second Fin FET transistors. The first Fin FET transistor includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET transistor includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section along the second direction and across the first gate electrode, the second gate electrode and the separation plug, the separation plug has a tapered shape having a top size smaller than a bottom size.

Abstract translation: 半导体器件包括第一和第二Fin FET晶体管和由绝缘材料制成并分布在第一和第二Fin FET晶体管之间的分离插头。 第一Fin FET晶体管包括在第一方向上延伸的第一鳍结构，形成在第一鳍结构上的第一栅极电介质和形成在第一栅极电介质上并且垂直于第一方向延伸的第二方向的第一栅电极。 第二鳍FET晶体管包括第二鳍结构，形成在第二鳍结构上的第二栅极电介质和形成在第一栅极电介质上并延伸第二方向的第二栅电极。 在沿着第二方向并横跨第一栅电极，第二栅电极和分离插塞的横截面中，分离插塞具有顶部尺寸小于底部尺寸的锥形形状。

公开(公告)号：US12125751B2

公开(公告)日：2024-10-22

申请号：US18157352

申请日：2023-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L23/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

公开(公告)号：US12080770B2

公开(公告)日：2024-09-03

申请号：US18065166

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/41791 ,  H01L21/265 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

公开(公告)号：US11929419B2

公开(公告)日：2024-03-12

申请号：US17129253

申请日：2020-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/762

CPC classification number: H01L29/4991 ,  H01L21/28088 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L21/0206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76224 ,  H01L29/4966

Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.