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    Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
    232.
    发明授权
    Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information 有权
    用于测量模型信号线的电气特性并提供测量信息的装置和方法

    公开(公告)号：US09318173B2

    公开(公告)日：2016-04-19

    申请号：US13946841

    申请日：2013-07-19

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C13/00 ,  G11C7/22 ,  G11C29/02 ,  G11C7/10

    CPC classification number: G06F17/5036 ,  G11C7/1066 ,  G11C7/227 ,  G11C13/0021 ,  G11C29/025

    Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

    Abstract translation: 用于测量模型信号线的电特性并且至少部分地基于电特性的测量提供测量信息的装置和方法。 示例性装置包括信号线模型，其包括被配置为模拟信号线的电特性的模型信号线。 该装置还包括耦合到信号线模型并被配置为响应于提供给模型信号线的输入信号来测量模型信号线的电特性的测量电路。 测量电路还被配置为至少部分地基于测量来提供测量信息，以设置施加到信号线的信号。

    Apparatuses including memory arrays with source contacts adjacent edges of sources
    233.
    发明授权
    Apparatuses including memory arrays with source contacts adjacent edges of sources 有权
    包括存储器阵列的设备，其中源触点邻近源的边缘

    公开(公告)号：US09263461B2

    公开(公告)日：2016-02-16

    申请号：US14200348

    申请日：2014-03-07

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: H01L27/115 ,  H01L27/24

    CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/249

    Abstract: Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.

    Abstract translation: 本文描述了包括三维（3D）存储器件和包括其的系统的各种装置。 在一个实施例中，3D存储器设备可以包括至少两个源; 至少两个存储器阵列分别形成并耦合到所述至少两个源; 以及源极导体，电源分别使用邻近所述源的一个或多个边缘的源极触点耦合到所述至少两个源。 所述至少两个存储器阵列中的每一个可以包括存储器单元，控制栅极和数据线。 在源的边缘和邻近边缘的源接触之间没有数据线。

    Short-checking methods
    235.
    发明授权
    Short-checking methods 有权
    短检方法

    公开(公告)号：US09136017B2

    公开(公告)日：2015-09-15

    申请号：US13922378

    申请日：2013-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C29/00 ,  G11C29/02 ,  G11C16/04 ,  G11C29/12

    CPC classification number: G11C29/50 ,  G01R31/025 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C29/025 ,  G11C29/08 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5004

    Abstract: In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage.

    Abstract translation: 在一个实施例中，短检查方法包括在激活耦合到数据线的存储器单元的同时将数据线充电到初始电压，从而允许数据线在继续激活存储器单元的同时浮动，感测数据上产生的电压 在一定时间之后，确定是否存在响应于所得电压的电平的短路。

    Interconnections for 3D memory
    236.
    发明授权
    Interconnections for 3D memory 有权
    3D存储器互连

    公开(公告)号：US09111591B2

    公开(公告)日：2015-08-18

    申请号：US13774522

    申请日：2013-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C5/06 ,  G11C5/02

    CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

    Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

    Abstract translation: 提供了用于3D存储器的互连的装置和方法。 一个示例性设备可以包括包括多对材料的材料堆叠，每对材料包括在绝缘材料上形成的导电线。 一叠材料具有在沿第一方向延伸的一个边缘处形成的阶梯结构。 每个阶梯步骤包括一对材料之一。 第一互连件耦合到阶梯级的导线，第一互连件在基本上垂直于楼梯台阶的第一表面的第二方向上延伸。

    Voltage generation and adjustment in a memory device
    237.
    发明授权
    Voltage generation and adjustment in a memory device 有权
    存储器件中的电压产生和调整

    公开(公告)号：US09025385B2

    公开(公告)日：2015-05-05

    申请号：US14041736

    申请日：2013-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C11/34 ,  G11C16/26 ,  G11C5/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30

    CPC classification number: G11C16/26 ,  G11C5/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30

    Abstract: Voltage generation devices and methods are useful in determining a data state of a selected memory cell in a memory device. Voltages can be generated in response to a first current and a second current. The first current is responsive to a memory device operation and a memory cell data state associated with the memory device operation, while the second current is responsive to a temperature associated with the memory device and to the memory cell data state associated with the memory device operation.

    Abstract translation: 电压产生装置和方法在确定存储器件中所选存储单元的数据状态时是有用的。 可以响应于第一电流和第二电流而产生电压。 第一电流响应于与存储器件操作相关联的存储器件操作和存储单元数据状态，而第二电流响应于与存储器件相关联的温度以及与存储器件操作相关联的存储器单元数据状态 。

    Sharing support circuitry in a memory
    238.
    发明授权
    Sharing support circuitry in a memory 有权
    在内存中共享支持电路

    公开(公告)号：US08995188B2

    公开(公告)日：2015-03-31

    申请号：US13864733

    申请日：2013-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C11/34 ,  G11C29/00 ,  G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/28

    Abstract: A memory device, system, and method for operation of a memory device. In one such memory device, the memory device comprises a plurality of strings of memory cells. A plurality of drain select devices are coupled to each string of memory cells. An upper drain select device shares common support circuitry (e.g., selecting/deselecting transistors) with one or more upper drain select devices of other strings of memory cells. The support circuitry (e.g., selecting/deselecting transistors) for lower drain select devices can also be shared between a plurality of strings of memory cells.

    Abstract translation: 用于存储器件操作的存储器件，系统和方法。 在一个这样的存储器件中，存储器件包括多个存储器单元串。 多个漏极选择装置耦合到每个存储单元串。 上漏极选择装置与其他存储器单元串的一个或多个上漏极选择装置共享公共支撑电路（例如，选择/取消选择晶体管）。 用于下排流选择器件的支持电路（例如，选择/取消选择晶体管）也可以在多个存储单元串之间共享。

    SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS
    239.
    发明申请
    SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS 有权
    具有多个层次的半导体器件和方法

    公开(公告)号：US20150021609A1

    公开(公告)日：2015-01-22

    申请号：US14511340

    申请日：2014-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: H01L27/115 ,  H01L21/02 ,  H01L29/49

    CPC classification number: H01L27/11582 ,  G11C8/10 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/495 ,  H01L29/4966

    Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

    Abstract translation: 公开了装置和方法，包括包括多个第一半导体材料层的装置，每个层包括至少一个存储单元的至少一个存取线和至少一个至少一个的至少一个源极，沟道和/或漏极 外围晶体管，例如在接入线解码器电路或数据线复用电路中使用的晶体管。 该装置还可以包括延伸穿过第一半导体材料层的第二半导体材料的多个支柱，每个支柱包括至少一个存储器单元的源极，沟道和/或漏极，或者在 至少一个外围晶体管。 还描述了形成这种装置的方法以及其他实施例。

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