公开(公告)号：US20200174954A1

公开(公告)日：2020-06-04

申请号：US16782023

申请日：2020-02-04

Applicant: Xilinx, Inc.

Inventor： Steven L. POPE

IPC: G06F13/362 ,  G06Q40/04 ,  G06F13/42 ,  G06F13/38

Abstract: A data processing system comprising: a host computer system supporting a software entity and a receive queue for the software entity; a network interface device having a controller unit configured to provide a data port for receiving data packets from a network and a data bus interface for connection to a host computer system, the network interface device being connected to the host computer system by means of the data bus interface; and an accelerator module arranged between the controller unit and a network and having a first medium access controller for connection to the network and a second medium access controller coupled to the data port of the controller unit, the accelerator module being configured to: on behalf of the software entity, process incoming data packets received from the network in one or more streams associated with a first set of one or more network endpoints; encapsulate data resulting from said processing in network data packets directed to the software entity; and deliver the network data packets to the data port of the controller unit so as to cause the network data packets to be written to the receive queue of the software entity.

公开(公告)号：US10673564B1

公开(公告)日：2020-06-02

申请号：US16138414

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Christopher H. Dick ,  William A. Wilkie

IPC: H04L1/00 ,  H03M13/29 ,  H03M13/45 ,  H03M13/11 ,  H04B1/38

Abstract: A modem includes an outer transceiver including a soft decision forward error correction (SD-FEC) circuit, wherein the SD-FEC circuit is hardwired and programmable to perform at least one of encoding or decoding data using a code type selected from a plurality of different code types, and an inner transceiver coupled to the SD-FEC circuit, wherein the inner transceiver is implemented in programmable circuitry.

公开(公告)号：US10673440B1

公开(公告)日：2020-06-02

申请号：US16539220

申请日：2019-08-13

Applicant: XILINX, INC.

Inventor： Rafael C. Camarota

IPC: H03K19/177 ,  G06F3/06 ,  G06F7/48 ,  H03K19/1776 ,  H03K19/17736 ,  H03K19/17724 ,  G06F7/483 ,  G06F7/502 ,  H03K19/17756

Abstract: Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.

公开(公告)号：US10673439B1

公开(公告)日：2020-06-02

申请号：US16367108

申请日：2019-03-27

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

Abstract: A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.

公开(公告)号：US10673438B1

公开(公告)日：2020-06-02

申请号：US16373524

申请日：2019-04-02

Applicant: Xilinx, Inc.

Inventor： Adam Elkins ,  Ephrem C. Wu ,  John M. Thendean ,  Adnan Pratama ,  Yashodhara Parulkar ,  Xiaoqian Zhang

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/17724 ,  G06F7/575 ,  H03K19/1776 ,  G06F7/501 ,  G06F7/523 ,  G06F7/48

Abstract: A digital signal processor (DSP) slice is disclosed. The DSP slice includes an input stage to receive a plurality of input signals, a pre-adder coupled to the input stage and configured to perform one or more operations on one or more of the plurality of input signals, and a multiplier coupled to the input stage and the pre-adder and configured to perform one or more multiplication operations on one or more of the plurality of input signals or the output of the pre-adder. The DSP slice further includes an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier. The ALU is configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, the output of the pre-adder, or the output of the multiplier. The DSP slice also includes an output stage coupled to the ALU, the output stage configured to generate one or more output signals based at least in part on one or more of the outputs of the ALU, or at least one of the plurality of input signals.

公开(公告)号：US10671779B1

公开(公告)日：2020-06-02

申请号：US16030686

申请日：2018-07-09

Applicant: Xilinx, Inc.

Inventor： Stephen A. Neuendorffer

IPC: G06F30/327

Abstract: A method of high level synthesis may include detecting in an application, using computer hardware, a first function including a first call site for a second function and a second call site for the second function, determining, using the computer hardware, that the first call site and the second call site each pass different data to the second function and each receive different return data from the second function, and generating, using the computer hardware, a circuit design from the application including a circuit block implementing the second function and multiplexer circuitry. The multiplexer circuitry may be configured to coordinate passing of data to the circuit block from a first source circuit corresponding to the first call site and a second source circuit corresponding to the second call site, with handshake signals exchanged between the circuit block, the first source circuit, and the second source circuit.

公开(公告)号：US10666777B2

公开(公告)日：2020-05-26

申请号：US16413413

申请日：2019-05-15

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  David James Riddoch ,  Kieran Mansley

IPC: H04L29/06 ,  H04L29/08 ,  H04L12/859

Abstract: A method of transmitting data for use at a data processing system and network interface device, the data processing system being coupled to a network by the network interface device, the method comprising: forming a message template in accordance with a predetermined set of network protocols, the message template including at least in part one or more protocol headers; forming an application layer message in one or more parts; updating the message template with the parts of the application layer message; processing the message template in accordance with the predetermined set of network protocols so as to complete the protocol headers; and causing the network interface device to transmit the completed message over the network.

公开(公告)号：US10664561B1

公开(公告)日：2020-05-26

申请号：US15729483

申请日：2017-10-10

Applicant: Xilinx, Inc.

Inventor： Pradip K. Kar ,  Satyaprakash Pareek ,  Shangzhi Sun ,  Bing Tian

IPC: G06F17/50

Abstract: Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.

公开(公告)号：US10656202B1

公开(公告)日：2020-05-19

申请号：US16137888

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Sing-Keng Tan ,  Xiaobao Wang ,  Andrew Tabalujan ,  Gubo Huang

IPC: G01R31/317 ,  G01R31/3185

Abstract: Examples of the present disclosure provide example devices that include an integrated circuit that has debugging capability. In some examples, a device includes an integrated circuit die. The integrated circuit die includes an input/output (IO) base cell and a debug port. The IO base cell has an interface node and a feedback node. The interface node is configured to be coupled to memory, such as via an interposer, for communication therebetween. The IO base cell is configurable to selectively output to the feedback node a signal that is on the interface node. The debug port has an input node and an output node. The input node is electrically connected to the feedback node. The debug port is configurable to selectively output to the output node a signal that is on the input node. The output node is configured to be coupled to a pin exterior to the integrated circuit die.

公开(公告)号：US10608641B2

公开(公告)日：2020-03-31

申请号：US16041602

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Hao Yu ,  Raymond Kong ,  Brian S. Martin ,  Jun Liu

IPC: G06F17/50 ,  G06F15/78 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17736 ,  H03K19/17728 ,  H03K19/177

Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.