公开(公告)号：US20160380030A1

公开(公告)日：2016-12-29

申请号：US14970347

申请日：2015-12-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract translation: 本公开涉及一种形成在晶片中的存储单元，其包括被第一绝缘层覆盖的半导体衬底，绝缘层被由半导体制成的有源层覆盖，所述存储单元包括具有控制栅极和第一绝缘层的选择晶体管 所述导电端子连接到可变电阻元件，所述栅极形成在所述有源层上并具有被第二绝缘层覆盖的侧面，所述可变电阻元件由可变电阻材料层形成，所述可变电阻材料层沉积在侧向 有源层的沿着栅极的侧面通过有源层形成的第一沟槽的侧面，沟槽导体形成在第一沟槽中，抵抗可变电阻材料层的侧面。

公开(公告)号：US09506964B2

公开(公告)日：2016-11-29

申请号：US13669741

申请日：2012-11-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G01R27/26 ,  G06F3/041 ,  G06F3/044

CPC classification number: G01R27/2605 ,  G06F3/0416 ,  G06F3/044

Abstract: The disclosure comprises: linking a first terminal of the capacitance to the mid-point of a first voltage divider bridge, applying a first voltage to a second terminal of the capacitance, maintaining a voltage of a mid-point of the first divider bridge near a reference voltage, and discharging a mid-point of a second divider bridge with a constant current. When a voltage of the mid-point of the second bridge reaches a first voltage threshold, applying a second voltage to the second terminal of the capacitance, and measuring the time for the voltage to reach a second threshold.

Abstract translation: 本公开包括：将电容的第一端子连接到第一分压器桥的中点，将第一电压施加到电容的第二端子，将第一分压器桥的中点的电压保持在 参考电压，并以恒定电流放电第二分频器桥的中点。 当第二桥的中点的电压达到第一电压阈值时，向电容的第二端施加第二电压，并测量电压达到第二阈值的时间。

公开(公告)号：US20160329932A1

公开(公告)日：2016-11-10

申请号：US15217430

申请日：2016-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Rizzo ,  Nathalie Vallespin ,  Emmanuel Papart

IPC: H04B5/00

CPC classification number: H04B5/0025 ,  H04B5/0043 ,  H04B5/0056

Abstract: A device includes near-field communication (NFC) control circuitry and transceiver circuitry. The transceiver circuitry is coupled to the NFC control circuitry. In a reader mode of operation, the NFC circuitry detects reception of NFC polling frames by the transceiver circuitry. When reception of an NFC polling frame is detected, the NFC control circuitry switches from the reader mode of operation to a card mode of operation.

Abstract translation: 一种设备包括近场通信（NFC）控制电路和收发器电路。 收发器电路耦合到NFC控制电路。 在读取器操作模式中，NFC电路通过收发器电路检测NFC轮询帧的接收。 当检测到NFC轮询帧的接收时，NFC控制电路从读取器操作模式切换到卡操作模式。

公开(公告)号：US20160315664A1

公开(公告)日：2016-10-27

申请号：US15198758

申请日：2016-06-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： ALEXANDRE TRAMONI ,  PIERRE RIZZO

IPC: H04B5/00 ,  H04W76/02 ,  H03H7/40

CPC classification number: H04B5/0031 ,  H03H7/40 ,  H04W76/14

Abstract: A first component (CMP1) is connected to the antenna (ANT) and to an impedance matching circuit (CAI) configurable on command and connected to the antenna, and in the absence of another component (CMP2) connected to the antenna, the impedance matching circuit is placed in a first configuration in which it forms with the first component and the antenna a resonant circuit having a first resonant frequency compatible with a carrier frequency. In the presence of a second component (CMP2) connected to the antenna, the impedance matching circuit is placed in a second configuration in which it forms with the first component, the second component and the antenna a resonant circuit having a second resonant frequency compatible with the carrier frequency.

Abstract translation: 第一组件（CMP1）连接到天线（ANT），并连接到根据命令配置并连接到天线的阻抗匹配电路（CAI），并且在没有连接到天线的另一组件（CMP2）的情况下，阻抗匹配 电路被放置在其中与第一部件形成的第一配置中，并且天线具有与载波频率兼容的第一谐振频率的谐振电路。 在存在连接到天线的第二组件（CMP2）的情况下，阻抗匹配电路被置于与第一组件，第二组件和天线形成的第二配置中，谐振电路具有与 载波频率。

公开(公告)号：US20160309176A1

公开(公告)日：2016-10-20

申请号：US14929129

申请日：2015-10-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jacques Talayssat ,  Sébastien Cleyet-Merle ,  Vitor Schwambach Costa

IPC: H04N19/426 ,  G06K9/26 ,  G06K9/62

CPC classification number: H04N19/426 ,  G06K9/00973 ,  G06K9/26 ,  G06K9/4614 ,  G06K9/6264 ,  G06K9/6285

Abstract: A method and device for real-time generation of a multiresolution representation of a digital image for real-time generation are disclosed. A sequence of main representations of the digital image is stored at successive different main resolutions in a main memory. A part of a current main representation is loaded from the main memory into a local memory via a bus. A current main representation is processed by determining a corresponding part of an intermediate representation of the image having an intermediate resolution lying between the resolution of the current main representation and the resolution of the subsequent main representation. The loading and processing steps are repeated for other parts of the current main representation until all parts of the current main representation have been successively loaded and processed.

Abstract translation: 公开了一种用于实时生成用于实时生成的数字图像的多分辨率表示的方法和装置。 数字图像的主要表示的序列被存储在主存储器中的连续不同的主分辨率上。 当前主表示的一部分通过总线从主存储器加载到本地存储器中。 通过确定具有位于当前主表示的分辨率和后续主表示的分辨率之间的中间分辨率的图像的中间表示的对应部分来处理当前主表示。 对当前主要表示的其他部分重复加载和处理步骤，直到当前主要表示的所有部分已被连续加载和处理。

公开(公告)号：US20160308011A1

公开(公告)日：2016-10-20

申请号：US15195784

申请日：2016-06-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Julien DELALLEAU ,  Arnaud REGNIER

IPC: H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/306 ,  H01L29/788 ,  G11C16/14

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US09472413B2

公开(公告)日：2016-10-18

申请号：US14451161

申请日：2014-08-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yoann Goasduff ,  Abderrezak Marzaki

IPC: H01L21/302 ,  H01L21/76 ,  H01L21/308 ,  H01L21/266 ,  H01L21/033

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/3085

Abstract: At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench.

Abstract translation: 在元件中形成至少一个突出块。 突出的块然后被第一覆盖层覆盖，以形成与突出块自对准的凹脊，并且其凹面朝向突出块。 然后以与脊和突出块两者自对准的方式在脊中形成第一沟槽。 第一沟槽延伸到到达突出块的深度。 使用脊和第一沟槽蚀刻突出块作为蚀刻掩模，以在与第一沟槽自对准的突出块中形成第二沟槽。 因此，通过限定第二沟槽的突出块的第二沟槽和未蚀刻部分产生图案。

公开(公告)号：US20160299797A1

公开(公告)日：2016-10-13

申请号：US14929106

申请日：2015-10-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Eric Bernasconi ,  David Coupe ,  Ludovic Chotard ,  Pierre-François Pugibet

IPC: G06F9/52 ,  G06F9/50

CPC classification number: G06F9/52 ,  G06F9/5016 ,  G06F9/5038 ,  G06F13/16

Abstract: An electronic device can be used for synchronizing tasks of an appliance that includes a memory access controller having inputs associated with priority levels. The device includes control circuits configured for receiving signals from events and delivering in response signals for activation of tasks. A configurable interface for external events designed to receive first event signals from at least one circuit of the appliance and to route some of them to the corresponding control circuits as a function of a first law of correspondence. A configurable interface for internal events designed to receive second event signals corresponding to the signals for activation of tasks and to route some of them to the control circuits as a function of a second law of correspondence.

Abstract translation: 电子设备可以用于同步设备的任务，该设备包括具有与优先级相关联的输入的存储器访问控制器。 该装置包括被配置用于从事件接收信号并递送响应信号以激活任务的控制电路。 用于外部事件的可配置接口，其被设计用于从设备的至少一个电路接收第一事件信号，并且将它们中的一些作为第一对应定律的函数将其路由到相应的控制电路。 用于内部事件的可配置接口，其被设计为接收与用于激活任务的信号相对应的第二事件信号，并将它们中的一些作为第二对应定律的函数将其路由到控制电路。

公开(公告)号：US09460808B2

公开(公告)日：2016-10-04

申请号：US14549291

申请日：2014-11-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard ,  Yohan Joly

IPC: H03K5/00 ,  G11C27/02 ,  G11C29/50 ,  G11C29/02 ,  H03K3/0231

CPC classification number: G11C27/024 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  H03K3/0231

Abstract: A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample and hold circuit of generates at least one main current representative of at least one leakage current of the switching module in its off state. The at least one main current is delivered to at least one auxiliary capacitor. An initial pulse signal is generated from the charging and discharging of the at least one auxiliary capacitor. The sampling phase of the sample and hold circuit is triggered at the rate of the pulses of a pulse signal derived from the initial pulse signal.

Abstract translation: 提供了一种用于控制采样和保持电路的方法，该采样和保持电路包括耦合到存储电容器的开关模块。 采样和保持电路外部的电路产生代表切换模块处于其关闭状态的至少一个泄漏电流的至少一个主电流。 至少一个主电流被传送到至少一个辅助电容器。 从至少一个辅助电容器的充电和放电产生初始脉冲信号。 采样和保持电路的采样相位以从初始脉冲信号得到的脉冲信号脉冲的速率被触发。

公开(公告)号：US09460761B2

公开(公告)日：2016-10-04

申请号：US14751701

申请日：2015-06-26

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francesco La Rosa

IPC: G11C11/34 ,  G11C7/00 ,  G11C7/02 ,  G11C5/14 ,  G11C7/06 ,  G11C7/08

CPC classification number: G11C7/065 ,  G11C7/08

Abstract: A sense amplifier includes: two detection inputs, a latch circuit including two sections coupled to each other and each supplying a data signal. Each section is respectively powered by a P-channel control transistor, having a gate terminal receiving a control signal linked to a respective detection input of the two detection inputs. The sense amplifier includes a control circuit configured to reduce each of the control signals to a sufficiently low voltage to put the corresponding control transistor to the on state, when the control signal reaches a reference voltage. The latch circuit is activated to supply one of the data signals when a corresponding one of the control transistors is in the on state.

Abstract translation: 读出放大器包括：两个检测输入端，一个锁存电路，包括彼此耦合的两个部分，并且各自提供一个数据信号。 每个部分分别由P沟道控制晶体管供电，其具有接收与两个检测输入的相应检测输入链接的控制信号的栅极端子。 读出放大器包括控制电路，其被配置为当控制信号达到参考电压时，将每个控制信号减小到足够低的电压以将相应的控制晶体管置于导通状态。 当对应的一个控制晶体管处于导通状态时，锁存电路被激活以提供数据信号之一。