公开(公告)号：US10075311B2

公开(公告)日：2018-09-11

申请号：US15686180

申请日：2017-08-25

Applicant: Silicon Motion Inc.

Inventor： Yain-Reu Lin

IPC: H04L7/00 ,  H04L27/01 ,  H04L1/24 ,  H04L7/033 ,  G06F13/40 ,  H04L7/04

CPC classification number: H04L27/01 ,  G06F13/40 ,  H04L1/242 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/041 ,  H04L25/03

Abstract: A clock correction method is provided. The clock correction method includes the following steps: receiving a training signal in a communication protocol, wherein the training signal carries a specific signal pattern occurring repeatedly; performing frequency division on the training signal according to a number of toggles of the specific signal pattern so as to generate an equalization training sequence clock; and correcting a frequency of an output clock of an oscillator according to the equalization training sequence clock.

公开(公告)号：US20180253259A1

公开(公告)日：2018-09-06

申请号：US15858066

申请日：2017-12-29

Applicant: Silicon Motion, Inc.

Inventor： Ming-Hung CHANG ,  Kuo-Yuan HSU

IPC: G06F3/06

Abstract: A data storage device in a two-layer control structure is provided. A control unit of the data storage device has a command processor and a first non-volatile memory (NVM) controller. The command processor is operative to communicate with a host. The first non-volatile memory (NVM) controller operates a first NVM of the data storage device. Earlier than the command processor operates according to a ROM image corresponding to the command processor, the first NVM controller operates according to a ROM image corresponding to the first NVM controller to access the first NVM to get a firmware image for the command processor and loads the command processor with the firmware image.

公开(公告)号：US10048870B2

公开(公告)日：2018-08-14

申请号：US15844890

申请日：2017-12-18

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng ,  Yu-Chih Lin

IPC: G11C7/00 ,  G06F3/06

Abstract: In one implementation, an electronic system includes a host and a data storage device. The data storage device includes a flash memory, a controller and a delay circuit. The controller is configured to receive a read command from the host, read a first data sector from the flash memory according to the read command, and produce a setting signal according to a maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit is configured to receive the setting signal from the controller, divide the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmit at least one of the first sub-data sectors to the host at a predetermined time interval for extending a busy time of the controller.

公开(公告)号：US10031698B2

公开(公告)日：2018-07-24

申请号：US15785325

申请日：2017-10-16

Applicant: Silicon Motion, Inc.

Inventor： Sheng-Liu Lin

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

Abstract: A method of wear leveling for a data storage device is provided. The data storage device includes a non-volatile memory having a plurality of blocks. A portion of the blocks not having any valid data are defined as spare blocks, and the spare blocks are associated with a spare pool. The method includes the steps of: maintaining a management table recording a plurality of physical block numbers and a plurality of block statuses corresponding to the blocks; selecting a first spare block having a first smallest physical block number as a current temporary block; receiving a write command from a host; determining whether data in the write command shall be written into the current temporary block; if false, selecting a second spare block having a second smallest physical block number as a next temporary block; and writing the data into the next temporary block.

公开(公告)号：US20180196747A1

公开(公告)日：2018-07-12

申请号：US15716587

申请日：2017-09-27

Applicant: Silicon Motion, Inc.

Inventor： Tao-En TANG

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/063 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: A mapping information rebuilding technique for a flash memory is introduced. Mapping information of data that has been stored in the flash memory is recorded in a plurality of logically-grouped tables. System information blocks are provided to store the mapping information by using the logically-grouped table as a management unit. A grouping list is stored in at least one pre-defined physical address of each system information block to list logical group numbers of the logically-grouped tables stored in the physical pages of the corresponding system information blocks. In each system information block, more physical pages are used in storing the logically-grouped tables than are used in storing the grouping list.

公开(公告)号：US20180196722A1

公开(公告)日：2018-07-12

申请号：US15662842

申请日：2017-07-28

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng Lin

IPC: G06F11/14 ,  G11C7/20 ,  G06F12/02 ,  G11C29/52

CPC classification number: G06F11/1469 ,  G06F11/0727 ,  G06F11/076 ,  G06F12/0246 ,  G06F12/0292 ,  G11C5/143 ,  G11C7/20 ,  G11C16/10 ,  G11C16/22 ,  G11C16/225 ,  G11C16/349 ,  G11C29/52 ,  G11C2029/0409

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller writes a data sector into a specific page of a specific block of the flash memory, and determines whether the specific block was undergoing a write operation at the time that a power-off event occurred after the data sector is written into the specific page, wherein the controller determines whether to read the data sector from the specific block according to whether the specific block was undergoing a write operation at the time that the power-off event occurred to confirm whether the data sector was successfully written into the specific page.

公开(公告)号：US10019355B2

公开(公告)日：2018-07-10

申请号：US15859724

申请日：2018-01-01

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G11C16/04 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0629 ,  G06F11/1072 ,  G06F11/108 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5641

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

公开(公告)号：US10019186B2

公开(公告)日：2018-07-10

申请号：US15692725

申请日：2017-08-31

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng Lin

IPC: G11C11/56 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.

公开(公告)号：US20180157417A1

公开(公告)日：2018-06-07

申请号：US15820727

申请日：2017-11-22

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen SHIH ,  Yen-Hung CHEN

IPC: G06F3/06 ,  G06F9/44

CPC classification number: G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F9/4405 ,  G06F13/42

Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a signal processing device. The processor accesses data stored in the data storage device via the predetermined interface. The signal processing device performs signal processing on the data. The processor transmits a first power mode change request packet to the data storage device via the predetermined interface, to request to change a data transfer speed of the predetermined interface from a first speed to a second speed. The processor receives a first power mode change confirm packet via the predetermined interface from the data storage device, and in response to the first power mode change confirm packet, the processor determines to keep the data transfer speed at the first speed and does not change the data transfer speed to the second speed.

公开(公告)号：US20180157309A1

公开(公告)日：2018-06-07

申请号：US15823328

申请日：2017-11-27

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen SHIH ,  Yen-Hung CHEN

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3253 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/068 ,  G06F13/1673 ,  G06F13/28 ,  Y02D10/154

Abstract: A data storage device coupled to a host device via a predetermined interface includes a memory device, an SRAM, and a controller. The controller is coupled to the memory device and the SRAM. The controller receives a first power mode change request packet requesting to change the data transfer speed of the predetermined interface from a first speed to a second speed via the predetermined interface from the host device, and in response to the first power mode change request packet, the controller determines whether the operation status of the data storage device is busy. When the operation status of the data storage device is busy, the controller determines to reject the request to change the data transfer speed and keeps the data transfer speed at the first speed and does not change the data transfer speed to the second speed.