中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

836 records (took 0.025 seconds)

    Phase interpolator
    262.
    发明授权
    Phase interpolator 有权

    公开(公告)号：US09673972B2

    公开(公告)日：2017-06-06

    申请号：US15283735

    申请日：2016-10-03

    Applicant: INPHI CORPORATION

    Inventor： James L. Gorecki ,  Jiayun Zhang ,  Marcial K. Chua ,  Cosmin Iorga

    IPC: H04L7/04 ,  H03K5/01 ,  H03K5/135 ,  H03L7/00 ,  H03L7/06 ,  H03L7/08 ,  H03K5/00

    CPC classification number: H04L7/04 ,  H03K5/01 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286 ,  H03L7/00 ,  H03L7/0807

    Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

    Eye scan for memory channel
    264.
    发明授权
    Eye scan for memory channel 有权

    公开(公告)号：US09665289B1

    公开(公告)日：2017-05-30

    申请号：US14959141

    申请日：2015-12-04

    Applicant: Inphi Corporation

    Inventor： Dat Tuan Mach ,  Alejandro Lopez-Sosa ,  Chao Xu ,  Chien-Hsin Lee

    IPC: G09F3/06 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F11/27

    CPC classification number: G06F3/061 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/067 ,  G06F11/27 ,  G06F13/1668 ,  G06F13/4068

    Abstract: Techniques are described for processing signal information from a high speed communication bus. The techniques include determining spatial regions on an eye by sampling a plurality of time and voltage points to determine a two-dimensional matrix. Then, the points are assigned a numerical value from combined time and voltage functions based upon a distance from eye edges (e.g., minimum setup time requirement and minimum hold time requirement along the time dimension). Sampling to generate the matrix may comprise selecting an initial point, splitting a first margin along a first dimension into equally spaced regions, and then sampling a second margin along a second dimension into equally spaced regions. Determining the points is based on shifting a strobe signal (DQS) position and a data signal (DQ) position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.

    Low power buffer with gain boost
    267.
    发明授权
    Low power buffer with gain boost 有权

    公开(公告)号：US09647643B2

    公开(公告)日：2017-05-09

    申请号：US15231449

    申请日：2016-08-08

    Applicant: INPHI CORPORATION

    Inventor： James Lawrence Gorecki ,  Han-Yuan Tan

    IPC: H03K3/012 ,  H03K5/02 ,  G11C27/02 ,  H03F1/32 ,  H03F3/45 ,  H03M1/12 ,  H03M3/00

    CPC classification number: H03K5/023 ,  G11C27/026 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03G3/20 ,  H03K3/012 ,  H03M1/1215 ,  H03M1/124 ,  H03M3/38 ,  H04B17/21

    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

    SYSTEM AND METHOD FOR CALIBRATION OF AN OPTICAL MODULE
    269.
    发明申请
    SYSTEM AND METHOD FOR CALIBRATION OF AN OPTICAL MODULE 有权

    公开(公告)号：US20170126313A1

    公开(公告)日：2017-05-04

    申请号：US15407163

    申请日：2017-01-16

    Applicant: INPHI CORPORATION

    Inventor： Todd ROPE

    IPC: H04B10/077 ,  H04B10/079

    CPC classification number: H04B10/0775 ,  H04B10/07955 ,  H04B10/07957 ,  H04B10/40

    Abstract: A system and method for calibrating an optical module. The optical module including a microprocessor with non-volatile memory is provided at a calibration station for measuring calibrated value of a device parameter against raw values starting from minimum value in each of multiple zones of a primary parameter with one or more secondary parameters at least being set to a basis calibration point to determine coefficients for generating a N-spline function for the multiple zones and multiple multipliers for each zone corresponding to multiple calibration points. The coefficients and multiple multipliers are stored in the non-volatile memory and reused respectively for calculating a basis calibrated value based on any current raw value of the primary parameter a N-spline function in particular zone and for determining a final multiplier by interpolation of the multiple multipliers associated with the one or more secondary parameters, leading to a calibrated value for any condition.

Patent Agency Ranking