公开(公告)号：US12148811B2

公开(公告)日：2024-11-19

申请号：US17810684

申请日：2022-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Chun Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method includes providing first and second structures over a substrate, wherein each of the first and second structures includes source/drain (S/D) regions, a channel region between the S/D regions, a sacrificial dielectric layer, and a sacrificial gate. The method further includes partially recessing the sacrificial gate without exposing the sacrificial dielectric layer in each of the first and the second structures; forming a first patterned mask that covers the first structure; removing the sacrificial gate from the second structure; removing the first patterned mask and the sacrificial dielectric layer from the second structure; and depositing a layer of a capacitor material over the portion of the sacrificial gate in the first structure and over the channel region in the second structure.

公开(公告)号：US12148620B2

公开(公告)日：2024-11-19

申请号：US18316307

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/28 ,  G03F7/09 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/02 ,  H01L21/027 ,  H01L21/30 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

公开(公告)号：US20240381788A1

公开(公告)日：2024-11-14

申请号：US18780824

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Min Lee ,  Shy-Jay Lin ,  Yen-Lin Huang ,  MingYuan Song ,  Tung Ying Lee

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01

Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.

公开(公告)号：US20240381786A1

公开(公告)日：2024-11-14

申请号：US18781095

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Yu-Feng Yin ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

公开(公告)号：US20240381668A1

公开(公告)日：2024-11-14

申请号：US18781094

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shy-Jay Lin ,  MingYuan Song ,  Hiroki Noguchi

IPC: H10B61/00 ,  H01L29/78 ,  H10N50/01 ,  H10N50/80

Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.

公开(公告)号：US20240381656A1

公开(公告)日：2024-11-14

申请号：US18783024

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H10B51/20 ,  G11C11/22 ,  G11C11/56 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US20240381621A1

公开(公告)日：2024-11-14

申请号：US18783146

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H10B12/00 ,  H01L21/02 ,  H01L21/225 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/94

Abstract: A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

公开(公告)号：US20240379851A1

公开(公告)日：2024-11-14

申请号：US18780748

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

公开(公告)号：US20240379850A1

公开(公告)日：2024-11-14

申请号：US18779489

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Shuan Li ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor method includes forming a fin-shaped structure extending from a substrate, the fin-shaped structure includes a number of channel layers interleaved by a number of sacrificial layers, recessing a source/drain region to form a source/drain opening, performing a PAI process to amorphize a portion of the substrate exposed by the source/drain opening, forming a tensile stress film over the substrate, performing an annealing process to recrystallize the portion of the substrate, the recrystallized portion of the substrate includes dislocations, forming an epitaxial source/drain feature over the source/drain opening, and forming a gate structure wrapping around each of the plurality of channel layers. By performing the above operations, dislocations are controllably and intentionally formed and carrier mobility in the number of channel layers may be advantageously enhanced, leading to improved device performance.

公开(公告)号：US20240379803A1

公开(公告)日：2024-11-14

申请号：US18784535

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju LEE ,  Zhi-Chang LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/786

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.