公开(公告)号：US20140312461A1

公开(公告)日：2014-10-23

申请号：US13866077

申请日：2013-04-19

Applicant: Commissariat A L'Energie Atomique Et Aux Energies Alternatives ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/761 ,  H01L29/06

CPC classification number: H01L21/2253 ,  H01L21/761 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract translation: 用于半导体制造的方法包括在半导体衬底中形成阱。 在阱内形成一个口袋，该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。 在p-n结处产生缺陷，使得p-n结的漏电阻减小。

公开(公告)号：US08860123B1

公开(公告)日：2014-10-14

申请号：US13852720

申请日：2013-03-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/792 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

公开(公告)号：US20140291842A1

公开(公告)日：2014-10-02

申请号：US13853784

申请日：2013-03-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Bernie Chrisanto ANG ,  Bryan Christian BACQUIAN

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).

Abstract translation: 将多芯片电子器件组装成薄电子封装的方法需要在中空衬底上反转倒装芯片布置，在中空衬底上堆叠另外的管芯以形成多芯片电子器件，并且封装多芯片 电子设备。 密封剂的封闭可以通过使用可移除的粘合剂膜连接分离的衬底部分或通过加强中空的整体衬底来实现。 使用可移除的粘合膜有助于用密封剂围绕多芯片电子器件。 粘合剂膜还可以防止密封剂在衬底周围爬行到支撑焊球垫的衬底的下侧，用于随后附接到球栅阵列（BGA）或焊盘栅阵列（LGA）。

公开(公告)号：US20140217938A1

公开(公告)日：2014-08-07

申请号：US14247955

申请日：2014-04-08

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.r.l.

Inventor： Frederic BONVIN ,  Ezio GALBIATI

IPC: H02P6/10

CPC classification number: H02P6/10 ,  G11B19/20 ,  H02P6/085 ,  H02P6/18

Abstract: An embodiment of a motor controller includes a motor driver and a signal conditioner. The motor driver is operable to generate a motor-coil drive signal having a first component at a first frequency, and the signal conditioner is coupled to the motor driver and is operable to alter the first component. For example, if the first component of the motor-coil drive signal causes the motor to audibly vibrate (e.g., “whine”), then the signal conditioner may alter the amplitude or phase of the first component to reduce the vibration noise to below a threshold level.

Abstract translation: 马达控制器的实施例包括马达驱动器和信号调节器。 马达驱动器可操作以产生具有第一频率的第一分量的电动机线圈驱动信号，并且信号调节器耦合到马达驱动器并且可操作以改变第一分量。 例如，如果电动机线圈驱动信号的第一分量使得电动机听起来振动（例如，“呜呜”），则信号调节器可以改变第一组件的幅度或相位，以将振动噪声降低到低于 门限等级。

公开(公告)号：US20140183735A1

公开(公告)日：2014-07-03

申请号：US13731878

申请日：2012-12-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： John H. ZHANG ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng XU ,  Walter Kleemeier ,  Cindy Goldberg

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract translation: 金属互连通过组合镶嵌工艺和减去金属蚀刻形成在一体中。 在电介质层中形成宽沟槽。 导电材料沉积在宽沟槽中。 在导电材料中蚀刻沟槽以描绘多个金属插塞，每个金属插头接触由宽沟槽暴露的相应金属轨道。

公开(公告)号：US20140170834A1

公开(公告)日：2014-06-19

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  STMicroelectronics S.A.

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US08729702B1

公开(公告)日：2014-05-20

申请号：US13682162

申请日：2012-11-20

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Chengyu Niu ,  Andrew Simon ,  Keith Kwong Hon Wong ,  Yun-Yu Wang

IPC: H01L23/40 ,  H01L21/82 ,  C23C14/00

CPC classification number: H01L23/481 ,  C23C14/046 ,  C23C14/34 ,  C23C14/3464 ,  H01L21/2855 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76873 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.

Abstract translation: 沟槽在电介质层中打开。 然后将沟槽衬有阻挡层和金属种子层。 金属种子层是非均匀掺杂的，并且表现出随沟槽深度变化的垂直掺杂梯度。 然后将衬里的沟槽填充有金属填充材料。 然后在金属填充的沟槽上沉积电介质盖层。 然后将来自非均匀掺杂的金属种子层的掺杂剂迁移到金属填充沟槽和电介质盖层之间的界面，以形成自对准金属帽。

公开(公告)号：US20140119268A1

公开(公告)日：2014-05-01

申请号：US14148047

申请日：2014-01-06

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W74/04 ,  H04W72/04 ,  H04W72/00

CPC classification number: H04W72/0446 ,  H04L12/43 ,  H04W72/005 ,  H04W74/04

Abstract: Methods and apparatus for implementing a robust unicast/broadcast/multicast protocol are provided. In one aspect, a method of avoiding collision of intra-basic service set unicast, broadcast or multicast transmissions notifies stations in the basic service set of a reserved transmit opportunity for a unicast, broadcast or multicast transmission. Transmissions from at least one station in the basic service set are deferred until after the reserved unicast, broadcast or multicast transmit opportunity.

Abstract translation: 提供了用于实现鲁棒的单播/广播/多播协议的方法和装置。 在一个方面，避免基本内部服务设置单播，广播或多播传输的冲突的方法通知用于单播，广播或多播传输的预留发送机会的基本服务集中的站。 基本服务集中的至少一个站的传输延迟到保留的单播，广播或多播发送机会之后。

公开(公告)号：US20140106529A1

公开(公告)日：2014-04-17

申请号：US14051174

申请日：2013-10-10

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Remi Beneyton

IPC: H01L29/66

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845

Abstract: A thermal annealing flow process includes the steps of: depositing a metal or metal alloy on a silicon semiconductor structure, performing a first annealing of a rapid thermal anneal (RTA) type to produce a metal rich phase in a portion of the silicon semiconductor structure, removing unreacted metal or metal alloy and performing a second annealing as a millisecond annealing at a temperature that is below a melt temperature of the silicon material present in the silicon semiconductor structure.

Abstract translation: 热退火流程包括以下步骤：在硅半导体结构上沉积金属或金属合金，执行快速热退火（RTA）型的第一退火以在硅半导体结构的一部分中产生富金相， 去除未反应的金属或金属合金，并在低于硅半导体结构中存在的硅材料的熔融温度的温度下进行第二退火作为毫秒退火。

公开(公告)号：US20140105098A1

公开(公告)日：2014-04-17

申请号：US14050575

申请日：2013-10-10

Applicant: STMICROELECTRONICS, INC.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04B7/155

CPC classification number: H04B7/15528 ,  H04W28/065

Abstract: A compressed header format is used for messages transmitted in a wireless network. The compressed header includes a first address field and a frame control field including at least one bit specifying whether the first address is for an access point of the wireless communications network. The frame control field may further include at least one additional bit identifying whether the frame is being relayed by a relay node positioned between the access point and a wireless station. The frame control field may further include at least one further bit identifying whether AID is used for the first address field.

Abstract translation: 压缩报头格式用于在无线网络中发送的消息。 压缩报头包括第一地址字段和帧控制字段，该字段包括指定第一地址是否用于无线通信网络的接入点的至少一个比特。 帧控制字段还可以包括至少一个附加位，标识帧是否被位于接入点和无线站之间的中继节点中继。 帧控制字段还可以包括至少一个识别是否将AID用于第一地址字段的另一位。