公开(公告)号：US10346346B1

公开(公告)日：2019-07-09

申请号：US15851449

申请日：2017-12-21

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F15/78 ,  G06F11/10 ,  G06F13/16 ,  G11C29/52

Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

公开(公告)号：US20190207687A1

公开(公告)日：2019-07-04

申请号：US15862058

申请日：2018-01-04

Applicant: Xilinx, Inc.

Inventor： Mayank Raj

IPC: H04B17/18 ,  H04B10/516

CPC classification number: H04B17/18 ,  H04B10/516

Abstract: An optical driver is disclosed, including a PMOS pull-up circuit, an NMOS pull-down circuit, and an inductive circuit. The PMOS pull-up circuit may include a first terminal to receive a first input signal based on a received data signal, and a P output terminal coupled to the inductive circuit. The NMOS pull-down circuit may include a second input terminal to receive a second input signal based on the received data signal, and an N output terminal coupled to the inductive circuit. The inductive circuit may include an L output terminal to output an output signal, a P coil coupled between the P output terminal and the L output terminal, and an N coil coupled between the N output terminal and the L output terminal. The P coil may be configured to hide a parasitic capacitance associated with the PMOS pull-up circuit during a falling edge transition of the received data signal, and the N coil may be configured to hide a parasitic capacitance associated with the NMOS pull-down circuit during a rising edge transition of the received data signal.

公开(公告)号：US10340898B1

公开(公告)日：2019-07-02

申请号：US15632236

申请日：2017-06-23

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov

IPC: H03K3/037 ,  H03K3/289 ,  H03K3/356 ,  H03K5/135 ,  H03K19/173

Abstract: The disclosed pulsed latched circuitry includes first and second latch circuits. The first and second latch circuits can be provided with additional logic circuit components to permit them to be operated as a flip-flop circuit, or as a FIFO circuit with a depth of two.

公开(公告)号：US10332885B1

公开(公告)日：2019-06-25

申请号：US15987722

申请日：2018-05-23

Applicant: Xilinx, Inc.

Inventor： Jing Jing

IPC: H01L23/522 ,  H01L27/108 ,  H01L29/76 ,  G11C11/24 ,  H01L27/10 ,  H01L27/105 ,  H01L49/02 ,  H01L27/02 ,  G06F17/50

Abstract: A capacitor includes a cell array including a plurality of cells and a fine tuning cell electrically coupled to the cell array by a first bus and a second bus. Each cell of the cell array includes a first number of fingers electrically coupled to the first and second bus, and a second number of fingers electrically coupled to the first and second bus. The fine tuning cell includes a third number of fingers electrically coupled to the first and second bus, and a fourth number of fingers electrically coupled to the first and second bus. The directional alignment of the first and second number of fingers is generally perpendicular, the directional alignment of the third and fourth number of fingers is generally perpendicular, and the second number of fingers is different than the fourth number of fingers.

公开(公告)号：US10331837B1

公开(公告)日：2019-06-25

申请号：US15354894

申请日：2016-11-17

Applicant: Xilinx, Inc.

Inventor： Jennifer D. McEwen ,  Ian L. McEwen ,  Chong M. Lee ,  Bart Reynolds

IPC: G06F17/50 ,  G06T11/20 ,  G06T11/60

Abstract: Rendering a graphical representation of an integrated circuit can include determining, using a processor, a tile of a device model at least partially within a viewport, determining, using the processor, an owning tile having a fly-over wire passing over the tile, determining, using the processor, a predetermined shape of the fly-over wire, and drawing, using the processor, the fly-over wire within the viewport based upon the shape.

公开(公告)号：US10320401B2

公开(公告)日：2019-06-11

申请号：US15784022

申请日：2017-10-13

Applicant: Xilinx, Inc.

Inventor： Augusto R. Ximenes ,  Bob W. Verbruggen ,  Christophe Erdmann

IPC: H03L7/091 ,  H03L7/099

Abstract: An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

公开(公告)号：US20190172504A1

公开(公告)日：2019-06-06

申请号：US15832515

申请日：2017-12-05

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  John K. Jennings ,  Edward Cullen ,  Ionut C. Cical ,  Darragh Walsh

IPC: G11C5/14 ,  G01K7/01 ,  G05F3/24

Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.

公开(公告)号：US10291501B1

公开(公告)日：2019-05-14

申请号：US15886688

申请日：2018-02-01

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: G11C7/00 ,  H04L12/26 ,  G11C7/10

Abstract: An integrated circuit (IC) includes a first device and a second device. A latency measurement circuit is configured to determine a first latency of the first device; and determine a second latency of the second device based on the first latency.

公开(公告)号：US10291239B1

公开(公告)日：2019-05-14

申请号：US16000698

申请日：2018-06-05

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Winson Lin ,  Parag Upadhyaya ,  Geoffrey Zhang ,  Kun-Yung Chang

IPC: H03L7/08 ,  H03L7/197

Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

公开(公告)号：US10289178B1

公开(公告)日：2019-05-14

申请号：US15479176

申请日：2017-04-04

Applicant: Xilinx, Inc.

Inventor： Adrian Lynam ,  John K. Jennings ,  Umanath R. Kamath ,  Michael J. Hart ,  James Karp

IPC: G01R19/00 ,  G06F1/20 ,  G05F1/46 ,  H03K17/22 ,  H03K19/003 ,  G01R19/165 ,  G01K13/00

Abstract: Methods and apparatus are described for detecting both single event latch-up (SEL) and electrical overvoltage stress (EOS) using a single, reconfigurable detection circuit. One example circuit capable of detecting a latch-up state and an overvoltage condition generally includes an impedance element coupled to a power supply node; a voltage divider coupled to the power supply node; a multiplexer having a first input coupled to a tap of the voltage divider, a second input coupled to a first portion of the impedance element, and a third input coupled to a second portion of the impedance element; a reference generator; and an analog-to-digital converter (ADC) having a first input coupled to an output of the multiplexer and a second input coupled to an output of the reference generator.