公开(公告)号：US10096606B1

公开(公告)日：2018-10-09

申请号：US15813471

申请日：2017-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L27/11 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/06 ,  H01L21/027

Abstract: In one example, the method includes removing a portion of at least a layer of a bottom spacer material positioned above a first bottom source/drain (S/D) region of a first vertical transistor so as to thereby form a gate-to-source/drain contact opening that exposes a portion of the first bottom S/D region, forming a continuous conductive gate electrode material layer above the first bottom S/D region and a second bottom S/D region and within the gate-to-source/drain contact opening, and removing a portion of the continuous gate electrode material layer so as to form first and second separate gate structures for the first and second vertical transistors, respectively, wherein a portion of the second gate structure is positioned within the gate-to-source/drain contact opening, thereby conductively coupling the second gate structure to the first bottom S/D region.

公开(公告)号：US10079308B1

公开(公告)日：2018-09-18

申请号：US15682631

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shesh Mani Pandey ,  Hui Zang ,  Josef S. Watts

IPC: H01L21/70 ,  H01L29/786 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/78642 ,  H01L21/76829 ,  H01L21/823412 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833

Abstract: The disclosure provides a vertical FinFET structure, including: a substrate including a first source/drain region; a looped channel region positioned on the first source/drain region of the substrate, the looped channel region having an inner perimeter which surrounds a hollow interior of the looped channel region; a first gate positioned within the hollow interior of the looped channel region, wherein the first gate is formed onto the looped channel region along the inner perimeter of the looped channel region; and a second source/drain region positioned on and overlying an upper surface of the looped channel region.

公开(公告)号：US20180254327A1

公开(公告)日：2018-09-06

申请号：US15694109

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L29/10 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/41741 ,  H01L21/28556 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

公开(公告)号：US09991363B1

公开(公告)日：2018-06-05

申请号：US15657594

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinsheng Gao ,  Haifeng Sheng ,  Jinping Liu ,  Huy Cao ,  Hui Zang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32105 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437

Abstract: A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.

公开(公告)号：US20180130711A1

公开(公告)日：2018-05-10

申请号：US15345612

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/66545

Abstract: A finFET includes a source or a drain including: a first semiconductor fin extending parallel to a second semiconductor fin, and a semiconductor connector fin creating a first semiconductor fin loop by connecting an end of the first semiconductor fin to an end of the second semiconductor fin. A diffusion break isolates the source or the drain, and is positioned about the first semiconductor connector fin and the ends of the first semiconductor fin and the second semiconductor fin. The semiconductor connector fin provides an epitaxial growth surface adjacent the diffusion break. A related method and IC structure are also disclosed.

公开(公告)号：US09876010B1

公开(公告)日：2018-01-23

申请号：US15342464

申请日：2016-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jagar Singh ,  Jerome Ciavatti

IPC: H01L23/62 ,  H01L27/06 ,  H01L23/522 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/0629 ,  H01L23/5226 ,  H01L23/5228 ,  H01L29/4232 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A resistor is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. The resistor is composed of a material suitable to provide a predetermined resistance to a current to be conducted therethrough. A pair of resistor contacts are electrically connected to the resistor and spaced to provide the predetermined resistance to the current.

公开(公告)号：US20180012839A1

公开(公告)日：2018-01-11

申请号：US15206361

申请日：2016-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/66 ,  H01L29/0653 ,  H01L29/785

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack.

公开(公告)号：US09853128B2

公开(公告)日：2017-12-26

申请号：US14735283

申请日：2015-06-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

公开(公告)号：US09847391B1

公开(公告)日：2017-12-19

申请号：US15479801

申请日：2017-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jae Gon Lee

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0646 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A substrate is provided that has a first conductivity type. A first semiconductor layer having a second conductivity type is formed on the substrate. A second semiconductor layer having the first conductivity type is formed on the first semiconductor layer. A field-effect transistor is formed that includes a fin having a plurality of nanosheet channel layers arranged in a vertical stack on the second semiconductor layer, and a gate structure wrapped about the nanosheet channel layers. The first semiconductor layer defines a first p-n junction with a portion of the substrate, and the second semiconductor layer defines a second p-n junction with the first semiconductor layer. The first p-n junction and the second p-n junction are arranged in vertical alignment with the gate structure and the nanosheet channel layers.

公开(公告)号：US09831346B1

公开(公告)日：2017-11-28

申请号：US15220990

申请日：2016-07-27

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L29/78 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L29/785 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/7682 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Fin field effect transistors (FinFETs) include air-gaps between adjacent metal contacts and/or between metal contacts and the transistor gate. The air-gaps are formed during non-conformal deposition of an isolation dielectric in conjunction with a metal-first process to form the conductive structures.