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79 条记录 (耗时 0.017 秒)

    Product for making isolated semiconductor structure
    21.
    发明授权
    Product for making isolated semiconductor structure 失效
    用于制造隔离半导体结构的产品

    公开(公告)号：US4630343A

    公开(公告)日：1986-12-23

    申请号：US773842

    申请日：1985-09-06

    申请人： John M. Pierce ,  William I. Lehrer

    发明人： John M. Pierce ,  William I. Lehrer

    IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  H01L23/31 ,  H01L21/461

    CPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/31604 ,  H01L21/76224 ,  H01L23/3178 ,  H01L2924/0002

    摘要： An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

    摘要翻译： 集成电路结构包括多个岛状半导体材料（16-1至16-5），每个岛通过围绕所述岛形成为环形的沟槽与相邻的岛分离，以横向限定每个这样的岛的尺寸，氧化物 （13-1至13-6）和所述岛的表面上形成的（12,14）和沉积在所述凹槽中的所述氧化物（14）上并且在所述装置的顶表面上的选定的玻璃（15） 所述玻璃具有其在半导体材料岛的掺杂剂基本上重新分布的温度以下的温度下流动的性质，所述选定的玻璃（15）具有基本上平坦的顶表面，从而使所述结构基本上平坦的顶表面。

    Test vector indexing method and apparatus
    22.
    发明授权
    Test vector indexing method and apparatus 失效
    测试向量索引方法和装置

    公开(公告)号：US4493045A

    公开(公告)日：1985-01-08

    申请号：US312839

    申请日：1981-10-19

    申请人： John H. Hughes, Jr.

    发明人： John H. Hughes, Jr.

    IPC分类号： G01R31/28 ,  G01R15/12 ,  G01R31/3183 ,  G01R31/319 ,  G05B19/02 ,  G05B23/02

    CPC分类号： G01R31/318371 ,  G01R31/31921

    摘要： A data channel for a digital tester includes a random access local memory containing a main vector sequence, a subroutine vector sequence, and a test vector list. An index register is loaded with the address of the first vector in the list of vectors that is to be inserted as a variable into a vector stream. A sequence instruction selects the index register as the source of a test vector address when a variable vector is to be inserted into the vector stream at a point in a subroutine. The sequence instruction also resets the index register to a state which determines the address of the next variable to be inserted into the test vector pattern.

    摘要翻译： 用于数字测试器的数据通道包括包含主向量序列，子程序向量序列和测试向量列表的随机存取局部存储器。 索引寄存器被加载到要作为变量插入到向量流中的向量列表中的第一向量的地址。 序列指令在子程序中的某个点将变量向量插入矢量流时，选择索引寄存器作为测试矢量地址的源。 序列指令还将索引寄存器复位为确定要插入到测试向量模式中的下一个变量的地址的状态。

    Impregnation of aluminum interconnects with copper
    24.
    发明授权
    Impregnation of aluminum interconnects with copper 失效
    铝互连铜浸渍

    公开(公告)号：US4489482A

    公开(公告)日：1984-12-25

    申请号：US501348

    申请日：1983-06-06

    申请人： Thomas Keyser ,  Michael E. Thomas ,  John M. Pierce ,  James M. Cleeves

    发明人： Thomas Keyser ,  Michael E. Thomas ,  John M. Pierce ,  James M. Cleeves

    IPC分类号： H01L23/52 ,  C23F1/00 ,  C23F1/18 ,  C23F1/20 ,  C23F4/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/92 ,  H01L21/285

    CPC分类号： C23F1/18 ,  C23F1/20 ,  C23F4/00 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76886

    摘要： A method for impregnating copper into aluminum interconnect lines on a semiconductor device is disclosed. In a first embodiment, an interconnect pattern is formed on an aluminum layer by etching while the aluminum is substantially free from copper, and the copper is thereafter introduced to the formed interconnect lines. In a second embodiment, copper is introduced to the aluminum layer prior to formation of the desired interconnect pattern. The copper-rich layer is removed from the areas to be etched prior to etching. The method facilitates chlorine plasma etching of the aluminum which is inhibited by the presence of copper. The method is also useful with various wet etching processes where the formation of a copper-rich layer is found to stabilize the aluminum layer during subsequent processing .

    摘要翻译： 公开了一种将铜浸入半导体器件中的铝互连线中的方法。 在第一实施例中，通过蚀刻在铝层上形成互连图案，同时铝基本上不含铜，然后将铜引入所形成的互连线。 在第二实施例中，在形成期望的互连图案之前将铜引入铝层。 在蚀刻之前，从要蚀刻的区域去除富铜层。 该方法促进了由于铜的存在而抑制的铝的氯等离子体蚀刻。 该方法对于各种湿法蚀刻工艺也是有用的，其中发现富铜层的形成在后续处理期间使铝层稳定。

    Method of making an integrated circuit bipolar memory cell
    25.
    发明授权
    Method of making an integrated circuit bipolar memory cell 失效
    制造集成电路双极存储单元的方法

    公开(公告)号：US4488350A

    公开(公告)日：1984-12-18

    申请号：US315678

    申请日：1981-10-27

    申请人： Madhukar B. Vora ,  William H. Herndon

    发明人： Madhukar B. Vora ,  William H. Herndon

    IPC分类号： H01L29/73 ,  G11C11/411 ,  H01L21/331 ,  H01L21/8229 ,  H01L27/06 ,  H01L27/102 ,  H01L21/225

    CPC分类号： H01L27/1025 ,  G11C11/4113 ,  H01L27/0688

    摘要： A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PN junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

    摘要翻译： 静态双极性随机存取存储单元包括在衬底中的外延硅袋41和42中形成的第一和第二晶体管。 晶体管的集电极19和19'以及基极15和15'与被掺杂以与所接触的区域的导电类型相匹配的多晶硅21互连。 由此产生的不期望的PN结40和40'使用金属硅化物25的上覆层短路。在覆盖N导电型多晶硅23或23'的区域中，去除金属硅化物并产生PN结37或37' 通过沉积P导电型多晶硅35c或35c'。 如果需要，可以在形成两个晶体管的基极区域的外延层的表面上沉积另外的P型多晶硅35a和35b以降低基极串联电阻。

    Dynamic TTL input comparator for CMOS devices
    26.
    发明授权
    Dynamic TTL input comparator for CMOS devices 失效
    用于CMOS器件的动态TTL输入比较器

    公开(公告)号：US4485317A

    公开(公告)日：1984-11-27

    申请号：US308073

    申请日：1981-10-02

    申请人： Thomas J. Davies, Jr.

    发明人： Thomas J. Davies, Jr.

    IPC分类号： H03K3/356 ,  H03K5/02 ,  H03K5/08 ,  H03K19/0185 ,  H03K19/094 ,  G01R19/165 ,  H03K5/24

    CPC分类号： H03K19/01855 ,  H03K3/356104

    摘要： A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "0" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with an input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

    摘要翻译： CMOS缓冲器，用于将TTL电平输入信号的动态转换转换为CMOS电平上的相应信号。 0.8伏最大TTL“0”输入电平与2.4伏最小“1”输入电平之间的参考电压由电容器之间的电荷分配产生。 该参考电平与由CMOS交叉耦合锁存器组成的动态比较器中的输入信号电平进行比较，以产生对应于TTL输入信号的CMOS电平的输出信号。

    Etching method
    27.
    发明授权
    Etching method 失效
    蚀刻方法

    公开(公告)号：US4484978A

    公开(公告)日：1984-11-27

    申请号：US535148

    申请日：1983-09-23

    申请人： Thomas Keyser

    发明人： Thomas Keyser

    IPC分类号： G03F7/09 ,  H01L21/311 ,  H01L21/768 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06 ,  C23F1/02

    CPC分类号： G03F7/094 ,  H01L21/31144 ,  H01L21/76804 ,  Y10S148/106

    摘要： The disclosure relates to techniques for etching layered materials to produce features with beveled edges, for example, wells in silicon oxide layers employed in integrated circuit fabrication. An anisotropic etch may be employed to form wells with vertical walls in the silicon oxide layer, and an isotropic etch may be employed to bevel peripheral corners of the walls. In preferred embodiments, a double mask of a photoresist layer on an underlying thin film may be used to define the limits of the anisotropic and isotropic etches, respectively.

    摘要翻译： 本公开涉及用于蚀刻层状材料以产生具有斜边缘的特征的技术，例如在集成电路制造中采用的氧化硅层中的阱。 可以使用各向异性蚀刻来形成在氧化硅层中具有垂直壁的阱，并且可以采用各向同性蚀刻来斜面壁的周边角。 在优选实施例中，下面的薄膜上的光致抗蚀剂层的双掩模可以分别用于限定各向异性蚀刻的极限。

    Tri-level input buffer
    29.
    发明授权
    Tri-level input buffer 失效
    三级输入缓冲区

    公开(公告)号：US4449065A

    公开(公告)日：1984-05-15

    申请号：US308070

    申请日：1981-10-02

    申请人： Thomas J. Davies, Jr.

    发明人： Thomas J. Davies, Jr.

    IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/096 ,  H03K19/20 ,  H03M5/16

    CPC分类号： H03K19/09425 ,  H03M5/16

    摘要： A simple six-transistor input buffer for generating and applying binary function test signals to associated circuitry in an integrated circuit package. The buffer recognizes three different voltage levels of an input signal that is applied to a single input test pin and generates three corresponding binary output signals that may be used for testing various functions of the associated circuitry.

    摘要翻译： 一个简单的六晶体管输入缓冲器，用于在集成电路封装中产生和应用二进制功能测试信号给相关电路。 缓冲器识别施加到单个输入测试引脚的输入信号的三个不同电压电平，并产生可用于测试相关电路的各种功能的三个相应的二进制输出信号。