中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

54 records (took 0.019 seconds)

    ANALOG TO DIGITAL CONVERTER WITH DITHER
    21.
    发明申请
    ANALOG TO DIGITAL CONVERTER WITH DITHER 有权
    模拟数字转换器与DITHER

    公开(公告)号：US20070109168A1

    公开(公告)日：2007-05-17

    申请号：US11273196

    申请日：2005-11-14

    Applicant: Michael Hennessy ,  Christopher Hurrell ,  Colin Lyden

    Inventor： Michael Hennessy ,  Christopher Hurrell ,  Colin Lyden

    IPC: H03M1/12

    CPC classification number: H03M1/0639 ,  H03M1/468

    Abstract: An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

    Abstract translation: 提供了一种模数转换器，包括用于对输入进行采样的电容器阵列，每个电容器具有至少一个相关联的开关，用于将电容器的端子可控地连接到第一参考电压或第二参考电压; 以及用于产生位序列的序列发生器，其中在对所述电容器阵列的输入进行采样期间，所述序列发生器的输出被提供给第一组电容器的开关，以控制所述第一组内的给定电容器是否为 通过其相关联的开关连接到第一参考电压或第二参考电压。

    Charge pump system for fast locking phase lock loop
    22.
    发明授权
    Charge pump system for fast locking phase lock loop 有权
    电荷泵系统，用于快速锁定锁相环

    公开(公告)号：US06897690B2

    公开(公告)日：2005-05-24

    申请号：US10874641

    申请日：2004-06-23

    Applicant: Michael F. Keaveney ,  Colin Lyden ,  Patrick Walsh

    Inventor： Michael F. Keaveney ,  Colin Lyden ,  Patrick Walsh

    IPC: F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101

    CPC classification number: H03K3/0231 ,  H03L7/0896

    Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

    Abstract translation: 用于快速锁定锁相环的电荷泵系统包括一组电荷泵单元; 以及控制逻辑电路，用于使所述一组n个电荷泵单元在宽带宽模式下产生具有标称电荷泵失配的上升和下降电荷脉冲; 并且在窄带宽模式下，使得n个电荷泵单元的至少一个子集能够顺序地产生与宽带宽模式中的标称电荷泵失配匹配的窄带宽模式中的平均电荷泵失配。

    Gain compensated fractional-N phase lock loop system and method
    23.
    发明申请
    Gain compensated fractional-N phase lock loop system and method 有权
    增益补偿分数N锁相环系统及方法

    公开(公告)号：US20050024152A1

    公开(公告)日：2005-02-03

    申请号：US10872626

    申请日：2004-06-21

    Applicant: Colin Lyden ,  Michael Keaveney ,  Patrick Walsh

    Inventor： Colin Lyden ,  Michael Keaveney ,  Patrick Walsh

    IPC: H03L7/00

    CPC classification number: H03L7/0898 ,  H03L7/1976 ,  H03L2207/04

    Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

    Abstract translation: 用于分数N相位锁相环的增益补偿技术包括：将N分频器反馈信号的参考信号锁定在包括相位检测器，电荷泵，环路滤波器和压控振荡器的锁相环中，在其反馈环路中使用N分频器 ; 用包括至少一个积分器的Σ-Δ调制器驱动N分频器以获得预定的分数N反馈信号; 并且通过预定因子来指令锁相环增益的缩放，并且通过所述因子对至少一个积分器的内容进行同步反比。

    Reduction of mismatch errors for multibit oversampled data converters
    24.
    发明授权
    Reduction of mismatch errors for multibit oversampled data converters 失效
    减少多位过采样数据转换器的失配误差

    公开(公告)号：US5986595A

    公开(公告)日：1999-11-16

    申请号：US810950

    申请日：1997-02-27

    Applicant: Colin Lyden ,  Aidan Keady

    Inventor： Colin Lyden ,  Aidan Keady

    IPC: H03M1/06 ,  H03M1/76

    CPC classification number: H03M1/0668 ,  H03M1/765 ,  H03M3/464 ,  H03M3/502

    Abstract: Mismatch errors within oversampled analog to digital (ADC) and digital to analog (DAC) data converters limit the overall conversion accuracy. A circuit is provided which interchanges the analog segments within a multibit oversampled converter in a fashion to move the mismatch errors away from the overall converter's passband frequencies and towards other frequencies where they do not interfere with the signal to be converted. The circuit works by minimizing the differences in the signals which control the individual segments. Circuits may be provided for achieving first, second and higher order "shaping" of the mismatch errors. The invention also provides a circuit in which exchange of the analog elements with the DACs of multibit oversampled converters is effected using a circular queue, so moving the mismatch errors to high frequency where they do not interfere with the signal to be converted.

    Abstract translation: 过采样模数（ADC）和数模（DAC）数据转换器中的不匹配误差限制了整体转换精度。 提供了一种电路，其以多位过采样转换器中的模拟段交换方式，以将失配误差移动离开整个转换器的通带频率，并朝着不干扰要转换的信号的其他频率移动。 该电路通过最小化控制各个段的信号的差异而起作用。 可以提供电路以实现失配误差的第一，第二和更高阶“成形”。 本发明还提供了一种电路，其中使用循环队列来实现模拟元件与多位过采样转换器的DAC的交换，从而将失配误差移动到高频，其中它们不干扰要转换的信号。

    IMPEDANCE MEASUREMENT DEVICE AND METHOD
    26.
    发明申请
    IMPEDANCE MEASUREMENT DEVICE AND METHOD 有权
    阻抗测量装置和方法

    公开(公告)号：US20130271155A1

    公开(公告)日：2013-10-17

    申请号：US13626434

    申请日：2012-09-25

    Applicant: Dermot O'Keeffe ,  Donal Bourke ,  David Harty ,  Tudor Vinereanu ,  Colin Lyden

    Inventor： Dermot O'Keeffe ,  Donal Bourke ,  David Harty ,  Tudor Vinereanu ,  Colin Lyden

    IPC: G01R27/02

    CPC classification number: G01R27/28

    Abstract: A digital sine wave may be converted to an analog signal at a digital to analog converter (DAC). The converted analog signal may be supplied to a device and an analog return signal from the device may be passed through a relaxed anti-aliasing filter and converted to digital code words at an analog to digital converter (ADC). An impedance may be calculated from the results of a Fourier analysis of the digital code words. The ADC and DAC clock frequencies may be asynchronous, independently variable, and have a greatest common factor of 1. The clock frequencies of the ADC and/or DAC may be adjusted to change a location of images in the ADC spectrum. By using these different, adjustable clock frequencies for the ADC and the DAC, an analog signal may have increased aliasing without introducing signal errors at a frequency of interest.

    Abstract translation: 数字正弦波可以在数模转换器（DAC）转换为模拟信号。 转换的模拟信号可以被提供给设备，并且来自设备的模拟返回信号可以通过松弛的抗混叠滤波器并且在模数转换器（ADC）处被转换成数字码字。 可以根据数字码字的傅立叶分析的结果来计算阻抗。 ADC和DAC时钟频率可以是异步的，可独立变化的，并且具有最大的共同因子1. ADC和/或DAC的时钟频率可以被调整以改变ADC频谱中图像的位置。 通过为ADC和DAC使用这些不同的可调时钟频率，模拟信号可能会增加混叠，而不会在感兴趣的频率下引入信号错误。

    Control Techniques for Motor Driven Systems
    27.
    发明申请
    Control Techniques for Motor Driven Systems 有权
    电机驱动系统的控制技术

    公开(公告)号：US20100202069A1

    公开(公告)日：2010-08-12

    申请号：US12555936

    申请日：2009-09-09

    Applicant: Colin LYDEN ,  Javier CALPE-MARAVILLA ,  Mark MURPHY ,  Eoin ENGLISH ,  Denis Martin O'CONNOR

    Inventor： Colin LYDEN ,  Javier CALPE-MARAVILLA ,  Mark MURPHY ,  Eoin ENGLISH ,  Denis Martin O'CONNOR

    IPC: G02B7/09 ,  G05B19/404

    CPC classification number: H02P23/0077

    Abstract: A drive signal for a motor-driven mechanical system has zero (or near zero) energy at an expected resonant frequency of the mechanical system. The drive signal may be provided in a series of steps according to a selected row of Pascal's triangle, wherein the number of steps equals the number of entries from the selected row of Pascal's triangle, each step has a step size corresponding to a respective entry of the selected row of Pascal's triangle, and the steps are spaced from each other according to a time constant determined by an expected resonant frequency of the mechanical system. Alternatively, the stepped drive signal may be provided as a series of uniform steps according to a selected row of Pascal's triangle, in which the steps are provided in a number of spaced intervals corresponding to the number of entries from the selected row of Pascal's triangle, each interval includes a number of steps corresponding to a respective entry from the selected row of Pascal's triangle and the intervals are spaced in time according to a time constant determined from the expected resonant frequency of the mechanical system. These techniques not only generate a drive signal with substantially no energy at the expected resonant frequency, they provide a zero-energy “notch” of sufficient width to tolerate systems in which the actual resonant frequency differs from the expected resonant frequencies.

    Abstract translation: 在机械系统的预期谐振频率下，用于电动机械系统的驱动信号具有零（或接近于零）的能量。 可以根据所选择的帕斯卡三角形行以一系列步骤提供驱动信号，其中步数等于所选行的帕斯卡三角形的条目数，每一步具有对应于 所选择的Pascal三角形行，并且步骤根据由机械系统的预期谐振频率确定的时间常数彼此间隔开。 或者，阶梯式驱动信号可以根据所选择的帕斯卡三角形行被提供为一系列均匀步骤，其中步骤以对应于所选行的帕斯卡尔三角形的条目数量的间隔间隔提供， 每个间隔包括对应于所选行的帕斯卡三角形的相应条目的多个步骤，并且间隔根据从机械系统的预期谐振频率确定的时间常数在时间上间隔开。 这些技术不仅在预期谐振频率下产生基本上没有能量的驱动信号，它们提供足够宽度的零能量“陷波”以容忍其中实际谐振频率与预期谐振频率不同的系统。

    Phase lock loop RF modulator system
    29.
    发明授权
    Phase lock loop RF modulator system 有权
    锁相环RF调制器系统

    公开(公告)号：US07420433B2

    公开(公告)日：2008-09-02

    申请号：US11494345

    申请日：2006-07-27

    Applicant: Cormac E. O'Sullivan ,  Colin Lyden ,  Hyman N. Shanan

    Inventor： Cormac E. O'Sullivan ,  Colin Lyden ,  Hyman N. Shanan

    IPC: H03C3/06

    CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991 ,  H03L7/1976

    Abstract: A phase lock loop RF modulator system including a phase lock loop circuit having a phase detector circuit responsive to an input reference signal and a feedback signal, an oscillator circuit responsive to the phase detector circuit for providing an output signal, a forward path from the phase detector circuit to the oscillator circuit, and a feedback path from the oscillator circuit to the phase detector circuit. The system also includes a first modulation port coupled to the feedback path, a second modulation port coupled to the forward path, and a gain mismatch detection circuit responsive to modulation data and a phase error between the reference signal and the feedback signal for providing an indicator output signal that represents the gain mismatch between the first modulation port and the second modulation port.

    Abstract translation: 一种锁相环RF调制器系统，包括一个锁相环电路，该电路具有响应于输入参考信号和反馈信号的相位检测器电路，响应相位检测器电路提供输出信号的振荡器电路，从相位 检测器电路到振荡器电路，以及从振荡器电路到相位检测器电路的反馈路径。 该系统还包括耦合到反馈路径的第一调制端口，耦合到正向通路的第二调制端口，以及响应于调制数据的增益失配检测电路和参考信号与反馈信号之间的相位误差，用于提供指示器 输出信号，其表示第一调制端口和第二调制端口之间的增益失配。

Patent Agency Ranking