公开(公告)号：US07948089B2

公开(公告)日：2011-05-24

申请号：US12100359

申请日：2008-04-09

Applicant: Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

Inventor： Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L23/525 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01049

Abstract: A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region.

Abstract translation: 提供了一种芯片堆叠封装，其中具有不同管芯尺寸的半导体芯片通过经由再分配工艺在划线区域中布置衬垫来堆叠，从而可以减小封装的厚度。 还提供了一种制造芯片堆叠封装的方法。 在芯片堆叠封装中，在基板的一个表面上布置多个电路图案，并且在其上安装单元半导体芯片。 单元半导体芯片包括顺序堆叠在基板上的多个半导体芯片。 单元半导体芯片的半导体芯片具有不同的管芯尺寸。 半导体芯片中的一个包括布置在第一芯片区域中的多个第一焊盘，并且其它半导体芯片包括布置在由划线区域限定的第二芯片区域的外侧的划线区域中的第二焊盘。

公开(公告)号：US20110111467A1

公开(公告)日：2011-05-12

申请号：US12904267

申请日：2010-10-14

Applicant: Sang Chul Lim ,  Moo Yong Uhm ,  Dae Won Lee ,  Hui Ho Kim ,  Dong Ho Lee ,  Hyun Seok Lee

Inventor： Sang Chul Lim ,  Moo Yong Uhm ,  Dae Won Lee ,  Hui Ho Kim ,  Dong Ho Lee ,  Hyun Seok Lee

IPC: C12P17/10 ,  C07D257/04

CPC classification number: C12P17/10 ,  C07D257/04

Abstract: Disclosed is a method for the preparation of carbamic acid (R)-1-aryl-2-tetrazolyl-ethyl esters, comprising the enantioselective enzyme reduction of a 1-aryl-2-tetrazolyl-ethyl ketone to form a (R)-1-aryl-2-tetrazolyl-ethyl alcohol and the carbamation of said alcohol.

Abstract translation: 公开了一种制备氨基甲酸（R）-1-芳基-2-四唑基乙基酯的方法，包括1-芳基-2-四唑基乙基酮的对映选择性酶还原形成（R）-1 芳基-2-四唑基乙醇和所述醇的氨基甲酸酯化。

公开(公告)号：US20110031621A1

公开(公告)日：2011-02-10

申请号：US12910260

申请日：2010-10-22

Applicant: Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

IPC: H01L23/48 ,  H01L23/535

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/01087

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract translation: 在具有应力消除间隔物的半导体器件封装及其制造方法中，从芯片本体延伸的金属互连指状物提供芯片互连。 金属手指通过应力消除间隔物与芯片的主体隔离。 在一个示例中，这种隔离采取气隙的形式。 在另一个实例中，这种隔离采用弹性体材料的形式。 在这两种情况下，都避免了金属互连指和芯体之间的热膨胀系数的不匹配，从而减轻了与开裂和分层相关的问题，从而提高了器件的产量和器件的可靠性。

公开(公告)号：US07880547B2

公开(公告)日：2011-02-01

申请号：US12711480

申请日：2010-02-24

Applicant: Chang-Ho Lee ,  Kyu Hwan An ,  Ki Seok Yang ,  Jaejoon Chang ,  Wangmyong Woo ,  Younsuk Kim ,  Haksun Kim ,  Ockgoo Lee ,  Dong Ho Lee ,  Hyungwook Kim ,  Joy Laskar

Inventor： Chang-Ho Lee ,  Kyu Hwan An ,  Ki Seok Yang ,  Jaejoon Chang ,  Wangmyong Woo ,  Younsuk Kim ,  Haksun Kim ,  Ockgoo Lee ,  Dong Ho Lee ,  Hyungwook Kim ,  Joy Laskar

IPC: H03F3/68

CPC classification number: H03F3/211 ,  H01F2017/0046 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/604 ,  H03F2200/451 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/21139 ,  H03F2203/21157 ,  H03F2203/45704 ,  H03F2203/45706 ,  H03F2203/45731 ,  Y10T29/49071

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Abstract translation: 可以为功率放大器系统提供系统和方法。 系统和方法可以包括多个功率放大器，其中每个功率放大器包括至少一个输出端口。 系统和方法还可以包括多个初级绕组，每个初级绕组具有第一圈数，其中每个初级绕组连接到多个功率放大器的至少一个输出端口，以及感应耦合到多个 初级绕组，其中次级绕组包括大于第一匝数的第二匝数。

公开(公告)号：US07834961B2

公开(公告)日：2010-11-16

申请号：US11616506

申请日：2006-12-27

Applicant: Yong-Ho Yang ,  Dong-Ho Lee

Inventor： Yong-Ho Yang ,  Dong-Ho Lee

IPC: G02F1/1335 ,  G09G3/36

CPC classification number: G02F1/133514 ,  G02F1/133555 ,  G02F2001/133357

Abstract: A color filter substrate is provided, including a substrate, a color filter layer formed on the substrate and including color filters where at least one of the color filters has an opening that partially exposes a portion of the substrate, a planarization layer reducing a step difference between the color filter layer and the portion of the substrate exposed by the opening, and a transparent electrode formed on the planarization layer.

Abstract translation: 提供一种滤色器基板，包括基板，形成在基板上的滤色器层，并且包括滤色器，其中至少一个滤色器具有部分地暴露基板的一部分的开口，平坦化层减小阶梯差 在所述滤色器层和由所述开口曝光的所述基板的所述部分之间，形成在所述平坦化层上的透明电极。

公开(公告)号：US20100207278A1

公开(公告)日：2010-08-19

申请号：US12769232

申请日：2010-04-28

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias.

Abstract translation: 公开了半导体封装结构。 半导体封装结构包括半导体衬底上的半导体芯片。 每个半导体芯片包括芯片焊盘。 贯通孔延伸穿过每个半导体芯片。 再分配结构和芯片选择互连线设置在每个半导体芯片上。 再分配结构将至少一个通孔与至少一个芯片焊盘电连接。 每个芯片选择互连线包括连接到对应数量的通孔的第一区域和将至少一个第一区域与其中一个芯片焊盘连接的第二区域。 半导体芯片使用贯通孔堆叠并电连接。

公开(公告)号：US20100108865A1

公开(公告)日：2010-05-06

申请号：US12613118

申请日：2009-11-05

Applicant: Seong-ho CHO ,  Dong-ho LEE

Inventor： Seong-ho CHO ,  Dong-ho LEE

IPC: G01N21/64 ,  G03F7/20

CPC classification number: G01N21/6452 ,  G01N21/6454 ,  G01N2021/6439 ,  G01N2021/6478 ,  G01N2035/00158

Abstract: A substrate for detecting samples includes; a body, and a plurality of micro lenses arranged on the body and configured for attachment to at least one sample, wherein the at least one sample emits fluorescent light, and wherein the plurality of micro lenses condense the fluorescent light emitted from the at least one sample via refraction.

Abstract translation: 用于检测样品的衬底包括： 主体和多个微透镜，其布置在主体上并且被配置为附接到至少一个样品，其中所述至少一个样品发射荧光，并且其中所述多个微透镜将从所述至少一个样品发射的荧光冷凝 样品通过折射。

公开(公告)号：US20100104638A1

公开(公告)日：2010-04-29

申请号：US12604560

申请日：2009-10-23

Applicant: WEI-GUO DAI ,  LIANG-CHANG DONG ,  TAE-HONG CHOI ,  SUNG JOO HWANG ,  JAE HYUN KIM ,  DONG HO LEE

Inventor： WEI-GUO DAI ,  LIANG-CHANG DONG ,  TAE-HONG CHOI ,  SUNG JOO HWANG ,  JAE HYUN KIM ,  DONG HO LEE

IPC: A61K9/22 ,  A61K31/16 ,  A61P19/00

CPC classification number: A61K9/2031 ,  A61K9/205 ,  A61K9/2054 ,  A61K9/2077 ,  A61K9/209 ,  A61K31/167 ,  A61K31/485 ,  A61K2300/00

Abstract: An extended release oral administered dosage form of acetaminophen and tramadol. The dosage form includes a composition of acetaminophen together with a tramadol complex formed with an anionic polymer. The tramadol complex provides sustained release of tramadol for a synchronized (coordinated) release profile of acetaminophen and tramadol.

Abstract translation: 对乙酰氨基酚和曲马多的延长释放口服给药剂型。 剂型包括对乙酰氨基酚组合物以及与阴离子聚合物形成的曲马多复合物。 曲马朵复合物提供曲马多的持续释放，用于对乙酰氨基酚和曲马多的同步（协调）释放曲线。

公开(公告)号：US07675365B2

公开(公告)日：2010-03-09

申请号：US11964646

申请日：2007-12-26

Applicant: Chang-Ho Lee ,  Kyu Hwan An ,  Ki Seok Yang ,  Jaejoon Chang ,  Wangmyong Woo ,  Younsuk Kim ,  Haksun Kim ,  Ockgoo Lee ,  Dong Ho Lee ,  Hyungwook Kim ,  Joy Laskar

Inventor： Chang-Ho Lee ,  Kyu Hwan An ,  Ki Seok Yang ,  Jaejoon Chang ,  Wangmyong Woo ,  Younsuk Kim ,  Haksun Kim ,  Ockgoo Lee ,  Dong Ho Lee ,  Hyungwook Kim ,  Joy Laskar

IPC: H03F3/68 ,  H03F1/00

CPC classification number: H03F3/211 ,  H01F2017/0046 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/604 ,  H03F2200/451 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/21139 ,  H03F2203/21157 ,  H03F2203/45704 ,  H03F2203/45706 ,  H03F2203/45731 ,  Y10T29/49071

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Abstract translation: 可以为功率放大器系统提供系统和方法。 系统和方法可以包括多个功率放大器，其中每个功率放大器包括至少一个输出端口。 系统和方法还可以包括多个初级绕组，每个初级绕组具有第一圈数，其中每个初级绕组连接到多个功率放大器的至少一个输出端口，以及感应耦合到多个 初级绕组，其中次级绕组包括大于第一匝数的第二匝数。

公开(公告)号：US07652383B2

公开(公告)日：2010-01-26

申请号：US11305282

申请日：2005-12-16

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

IPC: H01L23/29

CPC classification number: H01L25/105 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

Abstract translation: 提供一种不具有焊球的半导体封装模块和制造该半导体封装模块的方法。 该半导体封装模块包括：模块板，多个半导体器件能够安装在该模块板上;半导体封装，使用粘合剂结合在模块板上，可与模块板接合，并且已经经过电气最终测试 ，将所述半导体封装的第二接合焊盘与所述模块板的焊盘电连接的第二布线; 以及封装第二导线和半导体封装的第三密封树脂。 由于半导体封装模块不使用焊球，因此可以防止焊点可靠性（SJR）的劣化。 此外，使用已经经历电测试的半导体封装可以降低完成的半导体封装模块的产量的劣化。