公开(公告)号：US06833572B2

公开(公告)日：2004-12-21

申请号：US10229603

申请日：2002-08-27

Applicant: Fengyan Zhang ,  Tingkai Li ,  Hong Ying ,  Yoshi Ono ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Tingkai Li ,  Hong Ying ,  Yoshi Ono ,  Sheng Teng Hsu

IPC: H01L2976

CPC classification number: H01L28/75 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/55

Abstract: An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.

Abstract translation: 用于铁电体器件的电极包括底部电极; 铁电层 以及形成在强电介质层上并由金属组合形成的顶部电极，其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层，并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。 在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。

公开(公告)号：US06537361B2

公开(公告)日：2003-03-25

申请号：US09822637

申请日：2001-03-30

Applicant: Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

Inventor： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC: H01L2122

CPC classification number: H01L21/02197 ,  C01G21/00 ,  C01P2002/86 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/31604 ,  H01L21/31691

Abstract: A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2•3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185° C., and preferably no greater than 190° C. for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.

公开(公告)号：US06410346B1

公开(公告)日：2002-06-25

申请号：US10010186

申请日：2001-12-06

Applicant: Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

Inventor： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC: H01L2100

CPC classification number: H01L21/02197 ,  C23C16/40 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691

Abstract: A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

Abstract translation: 提供Pb3GeO5相PGO薄膜。 该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。 该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。 该方法在溶剂中混合Pd和锗。 将溶液加热以形成分解的前体蒸汽。 该方法提供沉积温度和压力。 沉积的膜也被退火以增强膜的铁弹性特征。 还提供了由本发明PGO膜制成的铁弹性电容器。

公开(公告)号：US07645669B2

公开(公告)日：2010-01-12

申请号：US11707712

申请日：2007-02-16

Applicant: Sheng Teng Hsu ,  Fengyan Zhang

Inventor： Sheng Teng Hsu ,  Fengyan Zhang

IPC: H01L21/336

CPC classification number: H01L29/94 ,  B82Y10/00 ,  H01L28/91 ,  H01L29/66083

Abstract: A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips.

Abstract translation: 提供了一种纳米尖端电容器和相关联的制造方法。 该方法提供底部电极并且生长覆盖底部电极的导电的纳米技术。 沉积覆盖在纳米尖端上的电绝缘电介质，并且将导电顶部电极沉积在覆盖有电介质的纳米尖端上。 通常，通过使用原子层沉积（ALD）工艺形成覆盖在纳米尖端上的介电层的薄层来沉积电介质。 在一个方面，覆盖纳米尖端的电绝缘电介质形成介电覆盖的纳米尖端的三维界面。 然后，覆盖介电覆盖的纳米尖端的导电顶部电极形成三维顶部电极接口，与介电覆盖的纳米尖端的第一个三维界面相匹配。

公开(公告)号：US20080191636A1

公开(公告)日：2008-08-14

申请号：US12042983

申请日：2008-03-05

Applicant: Sheng Teng Hsu ,  Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff

Inventor： Sheng Teng Hsu ,  Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff

IPC: H05B41/16 ,  H01J1/62

CPC classification number: H05B33/145

Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

Abstract translation: 提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。 通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面，Si磷光体层是SRSO层。 响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

公开(公告)号：US07402456B2

公开(公告)日：2008-07-22

申请号：US10831677

申请日：2004-04-23

Applicant: Wei-Wei Zhuang ,  Tingkai Li ,  Sheng Teng Hsu ,  Fengyan Zhang

Inventor： Wei-Wei Zhuang ,  Tingkai Li ,  Sheng Teng Hsu ,  Fengyan Zhang

IPC: H01L21/44

CPC classification number: H01L45/04 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

Abstract: A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.

Abstract translation: 提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。 该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。 在一个方面，第一晶体结构是无定形或弱结晶。 然后，响应于单极脉冲改变PCMO膜的电阻状态。 另一方面，PCMO薄膜具有多晶结构。 然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

公开(公告)号：US07148533B2

公开(公告)日：2006-12-12

申请号：US11226998

申请日：2005-09-14

Applicant: Sheng Teng Hsu ,  Fengyan Zhang

Inventor： Sheng Teng Hsu ,  Fengyan Zhang

IPC: H01L27/96

CPC classification number: G11C13/0007 ,  G11C2213/31 ,  H01L27/016 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641

Abstract: A memory cell and method for controlling the resistance properties in a memory material are provided. The method comprises: forming manganite; annealing the manganite in an oxygen atmosphere; controlling the oxygen content in the manganite in response to the annealing; and, controlling resistance through the manganite in response to the oxygen content. The manganite is perovskite-type manganese oxides with the general formula RE1-xAExMnOy, where RE is a rare earth ion and AE is an alkaline-earth ion, with x in the range between 0.1 and 0.5. Controlling the oxygen content in the manganite includes forming an oxygen-rich RE1-xAExMnOy region where y is greater than 3. A low resistance results in the oxygen-rich manganite region. When y is less than 3, a high resistance is formed. More specifically, the process forms a low resistance oxygen-rich manganite region adjacent an oxygen-deficient high resistance manganite region.

公开(公告)号：US06949435B2

公开(公告)日：2005-09-27

申请号：US10730726

申请日：2003-12-08

Applicant: Sheng Teng Hsu ,  Fengyan Zhang

Inventor： Sheng Teng Hsu ,  Fengyan Zhang

IPC: H01L21/28 ,  G11C11/15 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8239 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24 ,  H01L29/68 ,  H01L43/08 ,  H01L45/00 ,  H01L21/336

CPC classification number: H01L27/105 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/52 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

Abstract: An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method includes: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

Abstract translation: 提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。 该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。 在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。 通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

公开(公告)号：US06762063B2

公开(公告)日：2004-07-13

申请号：US10395368

申请日：2003-03-24

Applicant: Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

Inventor： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC: H01L2100

CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L29/78391

Abstract: A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode; depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.

Abstract translation: 制造非挥发性铁电存储晶体管的方法包括：形成底电极; 在超过底部电极的边缘的有源区域上沉积铁电层; 在铁电层上沉积顶部电极; 并且将该结构金属化以形成源电极，栅电极和漏电极。 非挥发性铁电存储晶体管包括形成在栅极区域上方的底部电极，其中底部电极在外围边界内具有预定区域; 延伸超过底部电极周边边界的铁电层; 以及形成在所述铁电层上的顶部电极。

公开(公告)号：US06759252B2

公开(公告)日：2004-07-06

申请号：US10621850

申请日：2003-07-16

Applicant: Fengyan Zhang ,  Sheng Teng Hsu ,  Hong Ying

Inventor： Fengyan Zhang ,  Sheng Teng Hsu ,  Hong Ying

IPC: H01L2102

CPC classification number: H01L28/55 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02266 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/67086 ,  H01L41/0533

Abstract: A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.

Abstract translation: 钝化层包括用于钝化铁电材料例如Pt / SBt / Ir-Ta-O器件的钛掺杂氧化铝层。 用于钝化铁电材料的钛掺杂氧化铝层具有减少的应力和改善的钝化性能，并且易于沉积并被氧化。 MFM结构中的钝化层在形成气体环境中抵抗器件退火过程中的击穿和剥离。