摘要:
An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.
摘要:
A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.
摘要:
A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.
摘要:
A method of forming an electrode in an integrated circuit includes preparing a silicon-base substrate, including forming semiconductor structures on the substrate to form an integrated substrate structure; depositing a layer of electrode material on a substrate structure; patterning the layer of electrode material to form electrode elements, wherein said patterning includes plasma etching the layer of electrode material in a plasma reactor in an etching gas atmosphere having a fluorine component therein; and cleaning the substrate structure and electrode elements in a distilled water bath.
摘要:
An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.
摘要:
A semiconductor structure includes, on a SOI substrate, a CMOS formed on the substrate; and a SiGe HBT formed on the substrate. A method of fabricating a semiconductor structure includes preparing a SOI substrate having plural active regions thereon; forming a CMOS on the SOI substrate in a first active region; and forming a SiGe HBT on the SOI substrate in another active region.
摘要:
A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.
摘要翻译:用于铁电非易失性存储器件的MFMOS单晶体管存储器结构包括诸如ZrO 2,HfO 2,Y 2 O 3或La 2 O 3等的高介电常数材料或其混合物,以减少操作电压并增加存储窗口, 设备的可靠性。
摘要:
A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.
摘要翻译:用于铁电非易失性存储器件的MFMOS单晶体管存储器结构包括诸如ZrO 2,HfO 2,Y 2 O 3或La 2 O 3等的高介电常数材料或其混合物,以减少操作电压并增加存储窗口, 设备的可靠性。
摘要:
Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.
摘要:
Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.