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    SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS
    21.
    发明申请
    SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS 有权

    公开(公告)号：US20210013150A1

    公开(公告)日：2021-01-14

    申请号：US17039187

    申请日：2020-09-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

    IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08

    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

    Scaled gate contact and source/drain cap
    24.
    发明授权
    Scaled gate contact and source/drain cap 有权

    公开(公告)号：US10892338B2

    公开(公告)日：2021-01-12

    申请号：US16169269

    申请日：2018-10-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Ruilong Xie ,  Jae Gon Lee

    IPC: H01L29/417 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

    Semiconductor structure including a varactor and method for the formation thereof
    25.
    发明授权
    Semiconductor structure including a varactor and method for the formation thereof 有权

    公开(公告)号：US10886419B2

    公开(公告)日：2021-01-05

    申请号：US15913344

    申请日：2018-03-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

    IPC: H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49 ,  H01L29/78 ,  H01L29/93 ,  H01L29/66

    Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.

    Titanium silicide formation in a narrow source-drain contact
    26.
    发明授权
    Titanium silicide formation in a narrow source-drain contact 有权

    公开(公告)号：US10854510B2

    公开(公告)日：2020-12-01

    申请号：US15687455

    申请日：2017-08-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Min Gyu Sung ,  Kwanyong Lim ,  Hiroaki Niimi

    IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/417 ,  H01L23/485

    Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.

    MULTIPLE PATTERNING WITH SELF-ALIGNMENT PROVIDED BY SPACERS
    29.
    发明申请
    MULTIPLE PATTERNING WITH SELF-ALIGNMENT PROVIDED BY SPACERS 审中-公开

    公开(公告)号：US20200350202A1

    公开(公告)日：2020-11-05

    申请号：US16400481

    申请日：2019-05-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiaoming Yang ,  Haiting Wang ,  Hong Yu ,  Jeffrey Chee ,  Guoliang Zhu

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/033

    Abstract: Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.

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