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公开(公告)号：US20110043235A1
公开(公告)日：2011-02-24
申请号：US12858673
申请日：2010-08-18
Applicant: Kab Yong Kim , Hyun Soon Jang , Yong Hwan Jeong
Inventor： Kab Yong Kim , Hyun Soon Jang , Yong Hwan Jeong
IPC: G01R1/067
CPC classification number: G01R31/2891 , G01R31/2884
Abstract: A semiconductor device includes a plurality of sensor pads configured to receive a probe signal from a testing apparatus, and a plurality of normal pads configured to receive a driving signal to drive the semiconductor device. In the plurality of sensor pads and the plurality of normal pads, a length in a direction corresponding to one of progress directions of a plurality of needles of the testing apparatus is longer than a length in another progress direction of the plurality of needles.
Abstract translation: 半导体器件包括被配置为从测试装置接收探测信号的多个传感器焊盘以及被配置为接收驱动信号以驱动半导体器件的多个正常焊盘。 在多个传感器焊盘和多个正常焊盘中，与测试装置的多个针的进给方向之一相对应的方向上的长度长于多个针的另一个进给方向上的长度。
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公开(公告)号：US07868438B2
公开(公告)日：2011-01-11
申请号：US12238894
申请日：2008-09-26
Applicant: Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
Inventor： Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
CPC classification number: H01L24/49 , G11C5/00 , G11C5/06 , H01L23/50 , H01L24/48 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014 , H01L2924/01006 , H01L2924/01055 , H01L2924/01075 , H01L2924/30105 , H01L2224/45099 , H01L2224/05599
Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.
Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。
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23.发明申请Parallel bit test apparatus and parallel bit test method capable of reducing test time 失效并行位测试装置和并行位测试方法，能够减少测试时间公开(公告)号：US20080168316A1
公开(公告)日：2008-07-10
申请号：US12003900
申请日：2008-01-03
Applicant: Yong-hwan Cho , Kwun-soo Cheon , Hyun-soon Jang , Seung-whan Seo
Inventor： Yong-hwan Cho , Kwun-soo Cheon , Hyun-soon Jang , Seung-whan Seo
CPC classification number: G11C29/40 , G11C5/04 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/2602
Abstract: A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.
Abstract translation: 包含在堆叠在多芯片封装（MCP）中并且共享一组数据信号线的存储器芯片中的并行位测试（PBT）装置可以包括：比较单元，用于输出表示比较的数据信号 分别提供给给定的一个存储器芯片的测试数据信号和从其输出的相应的数据信号之间; 以及编码单元，用于使用所述共享数据信号线组的第一子集输出所述代表数据信号，所述第一子集分别不与由所述存储器芯片中的其他存储器芯片对应的编码单元使用的其他子集重叠，所述编码单元选择 根据第一测试模式寄存器组（MRS）信号将数据信号线的共享数据集中的一个或多个数据信号线包括在第一子集中。
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公开(公告)号：US20070040280A1
公开(公告)日：2007-02-22
申请号：US11589192
申请日：2006-10-30
Applicant: Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
Inventor： Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
IPC: H01L23/52
CPC classification number: H01L24/49 , G11C5/00 , G11C5/06 , H01L23/50 , H01L24/48 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014 , H01L2924/01006 , H01L2924/01055 , H01L2924/01075 , H01L2924/30105 , H01L2224/45099 , H01L2224/05599
Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.
Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。
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公开(公告)号：US06751132B2
公开(公告)日：2004-06-15
申请号：US10108240
申请日：2002-03-26
Applicant: Hyun-Soon Jang , Jae-Hoon Kim
Inventor： Hyun-Soon Jang , Jae-Hoon Kim
IPC: G11C700
CPC classification number: G11C5/146
Abstract: A semiconductor memory device which provides an improved operation performance in response to a relatively low external power voltage is included. The device comprises a plurality of direct-current voltage generating circuits for generating a plurality of direct-current voltages and a plurality of reference voltage generating circuits for generating reference voltages for the plurality of the direct-current voltage generating circuits, respectively.
Abstract translation: 包括提供响应于相对较低的外部电源电压的改进的操作性能的半导体存储器件。 该装置包括用于产生多个直流电压的多个直流电压产生电路和用于分别产生多个直流电压产生电路的参考电压的多个参考电压发生电路。
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Patent Agency Ranking
公开(公告)号：US06560158B2
公开(公告)日：2003-05-06
申请号：US09981782
申请日：2001-10-17
Applicant: Jong-hyun Choi , Jei-hwan Yoo , Jong-eon Lee , Hyun-soon Jang
Inventor： Jong-hyun Choi , Jei-hwan Yoo , Jong-eon Lee , Hyun-soon Jang
IPC: G11C800
CPC classification number: G11C5/143
Abstract: A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode. Also provided is a semiconductor device, comprising: a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal: an auxiliary buffer for separately buffering the DPD enter/exit signal; a plurality of voltage generators for supplying operating voltages to internal circuit; DPD control circuit for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded, and to turn off the plurality of buffers excluding the auxiliary buffer; and an auto-pulse generator for generating a voltage pulse upon receiving the DPD exit command to initialize internal circuits of the semiconductor device.
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27.发明授权System for selecting one of a plurality of memory banks for use in an active cycle and all other banks for an inactive precharge cycle 失效用于选择在活动周期中使用的多个存储体组中的一个并用于无效预充电循环的所有其它存储体的系统
公开(公告)号：US5631871A
公开(公告)日：1997-05-20
申请号：US578151
申请日：1995-12-29
Applicant: Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
Inventor： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC: G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , B01F7/00 , B01F13/00
CPC classification number: G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。
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公开(公告)号：US08786303B2
公开(公告)日：2014-07-22
申请号：US12858673
申请日：2010-08-18
Applicant: Kab Yong Kim , Hyun Soon Jang , Yong Hwan Jeong
Inventor： Kab Yong Kim , Hyun Soon Jang , Yong Hwan Jeong
CPC classification number: G01R31/2891 , G01R31/2884
Abstract: A semiconductor device includes a plurality of sensor pads configured to receive a probe signal from a testing apparatus, and a plurality of normal pads configured to receive a driving signal to drive the semiconductor device. In the plurality of sensor pads and the plurality of normal pads, a length in a direction corresponding to one of progress directions of a plurality of needles of the testing apparatus is longer than a length in another progress direction of the plurality of needles.
Abstract translation: 半导体器件包括被配置为从测试装置接收探测信号的多个传感器焊盘以及被配置为接收驱动信号以驱动半导体器件的多个正常焊盘。 在多个传感器焊盘和多个正常焊盘中，与测试装置的多个针的进给方向之一相对应的方向上的长度比多个针的另一个进给方向上的长度长。
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29.发明申请Semiconductor memory device including post package repair control circuit and post package repair method 失效半导体存储器件包括后封装修复控制电路和后封装修复方法公开(公告)号：US20080247243A1
公开(公告)日：2008-10-09
申请号：US12080728
申请日：2008-04-04
Applicant: Jae-sung Kang , Byung-heon Kwak , Hyun-soon Jang , Seung-whan Seo , Sang-joon Ryu , Hyun-tae Lim
Inventor： Jae-sung Kang , Byung-heon Kwak , Hyun-soon Jang , Seung-whan Seo , Sang-joon Ryu , Hyun-tae Lim
CPC classification number: G11C29/70
Abstract: Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.
Abstract translation: 提供了一种具有后封装修复控制电路和后封装修复方法的半导体存储器件。 在半导体存储器件和后封装修复方法中，在后封装修复模式中，第二存储体被用作用于存储关于第一存储体的故障位信息的故障位图存储器，并且第一存储体被用作 用于存储关于第二存储体的失败位信息的故障位图存储器。
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30.发明授权Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method 失效半导体器件包括外部时钟的倍频器和测试数据的输出缓冲器以及半导体测试方法公开(公告)号：US06980036B2
公开(公告)日：2005-12-27
申请号：US10671105
申请日：2003-09-25
Applicant: Kyoung-hwan Kwon , Hyun-soon Jang , Kyu-hyoun Kim
Inventor： Kyoung-hwan Kwon , Hyun-soon Jang , Kyu-hyoun Kim
IPC: G06F1/04 , G11C11/40 , G11C29/00 , G11C29/12 , H03B1/00 , H03B19/00 , H03B19/10 , H03K5/00 , H03K5/1534 , H03K21/10
CPC classification number: H03K5/1534 , H03K5/00006
Abstract: In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier receives an external clock signal having a predetermined frequency and outputs an internal clock signal having greater frequency than the predetermined frequency. In the semiconductor device, the data output buffer outputs data tested in response to test data. Therefore, it is possible to test a plurality of memory cells at a time by using a clock signal having a low frequency. In addition, the time and cost required for the test can be greatly reduced, and conventional testing equipment that operates at a relatively low frequency can be effectively used.
Abstract translation: 在频率倍增器和将外部时钟信号的频率，数据输出缓冲器和包括倍频器和数据输出缓冲器的半导体器件相乘的方法中，倍频器接收具有预定频率的外部时钟信号并输出 具有比预定频率更大的频率的内部时钟信号。 在半导体器件中，数据输出缓冲器输出根据测试数据测试的数据。 因此，可以通过使用具有低频率的时钟信号来一次测试多个存储单元。 此外，可以大大降低测试所需的时间和成本，并且可以有效地使用在较低频率下工作的常规测试设备。
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