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21.发明申请SOLDERING CONNECTING PIN, SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD OF MOUNTING SEMICONDUCTOR CHIP USING THE SAME 审中-公开焊接连接引线，半导体封装基板及使用其安装半导体芯片的方法公开(公告)号：US20120127681A1
公开(公告)日：2012-05-24
申请号：US13010709
申请日：2011-01-20
Applicant: Ji Man RYU , Kwan Ho LEE , Kyu Bum HAN , Seog Moon CHOI , Jin Su KIM
Inventor： Ji Man RYU , Kwan Ho LEE , Kyu Bum HAN , Seog Moon CHOI , Jin Su KIM
CPC classification number: H05K3/306 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/13017 , H01L2224/1601 , H01L2224/16057 , H01L2224/16058 , H01L2224/16059 , H01L2224/1607 , H01L2224/16235 , H01L2224/16501 , H01L2224/811 , H01L2224/81193 , H01L2224/81385 , H01L2224/81447 , H01L2224/81815 , H01L2224/81899 , H01L2224/81906 , H01L2224/8192 , H01L2224/81951 , H01L2224/81986 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/351 , H05K3/3447 , H05K2201/10166 , H05K2201/10401 , Y10T29/49155 , H01L2924/00014 , H01L2924/00
Abstract: Disclosed herein are a soldering connecting pin, a semiconductor package substrate and a method of mounting a semiconductor chip using the same. A semiconductor chip is mounted on the printed circuit board using the soldering connecting pin inserted into a through-hole of the printed circuit board, thereby preventing deformation of the semiconductor package substrate and fatigue failure due to external shocks.
Abstract translation: 这里公开了一种焊接连接引脚，半导体封装基板和使用该半导体封装基板的半导体芯片的安装方法。 使用插入印刷电路板的通孔中的焊接连接销将半导体芯片安装在印刷电路板上，从而防止半导体封装基板的变形和由于外部冲击引起的疲劳失效。
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公开(公告)号：US20110042042A1
公开(公告)日：2011-02-24
申请号：US12581129
申请日：2009-10-17
Applicant: Jong Man KIM , Seog Moon Choi , Sang Hyun Shin , Jin Su Kim
Inventor： Jong Man KIM , Seog Moon Choi , Sang Hyun Shin , Jin Su Kim
CPC classification number: F28F1/08 , F21V29/51 , F21Y2115/10 , F21Y2115/30 , F28D15/0275 , F28F2275/025 , F28F2275/14 , H01L2924/0002 , H01L2924/00
Abstract: Disclosed herein is a radiating package module for an exothermic element. The radiating package module includes a heat conducting plate which has a groove of an internal thread shape, with the exothermic element being mounted on a surface of the heat conducting plate. A heat pipe is inserted into the groove in a screw-type coupling manner and has a coupling part of an external thread shape. An adhesive is applied between the groove and the coupling part. A cooling unit is coupled to an end of the heat pipe. The radiating package module maintains the reliability with which the radiating package radiates heat and improves structural reliability.
Abstract translation: 本文公开了用于放热元件的辐射封装模块。 辐射封装模块包括具有内螺纹形状的槽的导热板，放热元件安装在导热板的表面上。 热管以螺旋式联接的方式插入凹槽中并具有外螺纹形状的联接部分。 在凹槽和耦合部分之间施加粘合剂。 冷却单元联接到热管的一端。 辐射封装模块保持辐射封装散热的可靠性，提高结构可靠性。
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公开(公告)号：USD631464S1
公开(公告)日：2011-01-25
申请号：US29364747
申请日：2010-06-28
Applicant: Jin Su Kim
Designer： Jin Su Kim
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公开(公告)号：US11151802B2
公开(公告)日：2021-10-19
申请号：US14001037
申请日：2012-02-09
Applicant: Heung-san Choi , Jin-su Kim , Young-guk Park , Seung-hak Baek , Sang-hwan Joo , Hyung-jun Cho
Inventor： Heung-san Choi , Jin-su Kim , Young-guk Park , Seung-hak Baek , Sang-hwan Joo , Hyung-jun Cho
Abstract: The present invention relates to a method and system for providing a face adjustment image, the method comprising the steps of: (a) generating a matched image by superimposing a cephalometric image having a cranium image of a patient whose face is to be corrected with a three-dimensional facial image of the patient; and (b) displaying a predicted facial image on a screen by transforming soft skin tissues of the face according to the skeletal change in the cephalometric image. According to the present invention, the change in the soft skin tissues and the predicted facial image are displayed on a screen of a computer, a terminal or the like based on the skeletal change in cranium, teeth, prosthesis or the like supporting the soft skin tissues. Therefore, the change in the soft skin tissues can be predicted, thereby increasing the accuracy of a face correction operation, making it more accurate and convenient to plan the operation, and enhancing communication between the patient and medical staff.
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公开(公告)号：US09532462B2
公开(公告)日：2016-12-27
申请号：US13512271
申请日：2010-11-25
Applicant: Yeong Uk Seo , Sung Woon Yoon , Jin Su Kim , Myoung Hwa Nam , Sang Myung Lee , Chi Hee Ahn
Inventor： Yeong Uk Seo , Sung Woon Yoon , Jin Su Kim , Myoung Hwa Nam , Sang Myung Lee , Chi Hee Ahn
CPC classification number: H05K3/101 , H05K1/02 , H05K1/0353 , H05K1/092 , H05K3/02 , H05K3/108 , H05K3/20 , H05K2201/0376 , H05K2203/0278
Abstract: The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.
Abstract translation: 本发明提供一种印刷电路板的结构及其制造方法。 该方法包括：（a）在形成种子层的绝缘层上形成电路图形; （b）通过压制方法将电路图案嵌入绝缘层; 和（c）去除种子层。 根据本发明，可以通过在绝缘层上直接形成电路图案而形成不发生取向问题的精细图案，并且通过执行将突出电路嵌入绝缘层中的工艺可以提高形成的精细图案的可靠性。 此外，通过在去除种子层的蚀刻工艺期间，通过在电路层上过度蚀刻比低于绝缘层的表面的电路层，由于相邻电路之间的离子迁移而发生劣质电路的可能性可能会降低。
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Patent Agency Ranking
公开(公告)号：US08956962B2
公开(公告)日：2015-02-17
申请号：US13242331
申请日：2011-09-23
Applicant: Young-Jae Lee , Kyoung Jong Yoo , Jin Su Kim , Jun Lee , Yong In Lee , JunBo Yoon , JeongHo Yeon , Joo-Hyung Lee , Jeong Oen Lee
Inventor： Young-Jae Lee , Kyoung Jong Yoo , Jin Su Kim , Jun Lee , Yong In Lee , JunBo Yoon , JeongHo Yeon , Joo-Hyung Lee , Jeong Oen Lee
IPC: H01L21/40 , H01L21/033 , B82Y10/00
CPC classification number: H01L21/0337 , B82Y10/00 , H01L21/0338 , Y10S438/947
Abstract: A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area.
Abstract translation: 一种制造大面积纳米级图案的方法包括：形成由钝化层隔离的多层主薄膜; 图案化第一主薄膜以形成第一主图案; 相对于所述第一主图形形成第一间隔图案; 以及通过将第一间隔图案转印到第二主薄膜上而形成第二主图案。 通过使用由不同钝化膜分离的多层主薄膜，可以重复地进行能够减小图案间距的间隔光刻，并且在形成微米尺度图案之后，图案间距重复减小而没有形状变形，从而形成纳米级精细图案 均匀地在广泛的地区。
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公开(公告)号：US20130112463A1
公开(公告)日：2013-05-09
申请号：US13512271
申请日：2010-11-25
Applicant: Yeong Uk Seo , Sung Woon Yoon , Jin Su Kim , Myoung Hwa Nam , Sang Myung Lee , Chi Hee Ahn
Inventor： Yeong Uk Seo , Sung Woon Yoon , Jin Su Kim , Myoung Hwa Nam , Sang Myung Lee , Chi Hee Ahn
CPC classification number: H05K3/101 , H05K1/02 , H05K1/0353 , H05K1/092 , H05K3/02 , H05K3/108 , H05K3/20 , H05K2201/0376 , H05K2203/0278
Abstract: The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.
Abstract translation: 本发明提供一种印刷电路板的结构及其制造方法。 该方法包括：（a）在形成种子层的绝缘层上形成电路图形; （b）通过压制方法将电路图案嵌入绝缘层; 和（c）去除种子层。 根据本发明，可以通过在绝缘层上直接形成电路图案而形成不发生取向问题的精细图案，并且通过执行将突出电路嵌入绝缘层中的工艺可以提高形成的精细图案的可靠性。 此外，通过在去除种子层的蚀刻工艺期间，通过在电路层上过度蚀刻比低于绝缘层的表面的电路层，由于相邻电路之间的离子迁移而发生劣质电路的可能性可能会降低。
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28.发明申请SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME 失效半导体封装及其制造方法和具有该半导体元件的半导体封装模块公开(公告)号：US20130105955A1
公开(公告)日：2013-05-02
申请号：US13361144
申请日：2012-01-30
Applicant: Jin Su Kim , Ji Man Ryu , Soon Gyu Yim
Inventor： Jin Su Kim , Ji Man Ryu , Soon Gyu Yim
IPC: H01L23/495 , H01L21/50 , H01L23/48
CPC classification number: H01L24/83 , H01L23/3121 , H01L23/49503 , H01L23/49513 , H01L23/49524 , H01L23/49531 , H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/00014 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/18301 , H01L2924/19107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
Abstract: Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.
Abstract translation: 本文公开了一种半导体芯片，包括：在其一个表面上形成有凹部的第一基板和形成在凹部的底表面上的开口; 与第一基板的另一个表面接触的第二基板; 以及安装在凹部中的半导体芯片。
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公开(公告)号：US20130062106A1
公开(公告)日：2013-03-14
申请号：US13512748
申请日：2010-11-26
Applicant: Jin Su Kim , Duk Nam Kim , Jae Hyun Ahn , Sang Myung Lee , Yeong Uk Seo , Chi Hee Ahn , Sung Woon Yoon , Myoung Hwa Nam
Inventor： Jin Su Kim , Duk Nam Kim , Jae Hyun Ahn , Sang Myung Lee , Yeong Uk Seo , Chi Hee Ahn , Sung Woon Yoon , Myoung Hwa Nam
CPC classification number: H05K3/4658 , H05K3/205 , H05K3/4007 , H05K3/4647 , H05K2203/0108 , Y10T29/49155
Abstract: A structure of a printed circuit board and a method of manufacturing the same are provided. The manufacturing method includes a first step of forming at least one connecting bump on first circuit patterns and forming a first insulating layer to form an inner circuit board, a second step of processing a second insulating layer with a metal seed layer formed thereon using a mold to form second circuit patterns so as to construct an outer circuit board, and a third step of aligning the inner circuit board and the outer circuit board with each other and laminating the inner circuit board and the outer circuit board. Accordingly, a structure of a high-density high-reliability printed circuit board having a circuit embedded in an insulating layer can be provided. A seed layer forming process for forming an outmost circuit can be removed by using an insulating layer combined with a seed layer. In addition, a conductive structure in the form of a connecting bump is formed, and thus a complicated process of forming a via-hole and filling the via-hole with a conductive material is not required. Furthermore, a process of grinding the surface of the filled conductive material is removed so as to remarkably decrease a circuit error rate.
Abstract translation: 提供一种印刷电路板的结构及其制造方法。 该制造方法包括：在第一电路图案上形成至少一个连接凸块并形成第一绝缘层以形成内部电路板的第一步骤;使用模具处理其上形成有金属晶种层的第二绝缘层的第二步骤 以形成第二电路图案以构成外部电路板，以及将内部电路板和外部电路板彼此对准并层压内部电路板和外部电路板的第三步骤。 因此，可以提供具有嵌入在绝缘层中的电路的高密度高可靠性印刷电路板的结构。 可以通过使用与种子层结合的绝缘层来去除用于形成最外层电路的籽晶层形成工艺。 此外，形成连接凸块形式的导电结构，因此不需要形成通孔并且用导电材料填充通孔的复杂工艺。 此外，去除了填充的导电材料的表面的研磨过程，以显着降低电路错误率。
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公开(公告)号：US20120156882A1
公开(公告)日：2012-06-21
申请号：US13242331
申请日：2011-09-23
Applicant: YOUNG-JAE LEE , KYOUNG JONG YOO , JIN SU KIM , JUN LEE , YONG IN LEE , JUNBO YOON , JEONGHO YEON , JOO-HYUNG LEE , JEONG OEN LEE
Inventor： YOUNG-JAE LEE , KYOUNG JONG YOO , JIN SU KIM , JUN LEE , YONG IN LEE , JUNBO YOON , JEONGHO YEON , JOO-HYUNG LEE , JEONG OEN LEE
IPC: H01L21/308
CPC classification number: H01L21/0337 , B82Y10/00 , H01L21/0338 , Y10S438/947
Abstract: A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area.
Abstract translation: 一种制造大面积纳米级图案的方法包括：形成由钝化层隔离的多层主薄膜; 图案化第一主薄膜以形成第一主图案; 相对于所述第一主图形形成第一间隔图案; 以及通过将第一间隔图案转印到第二主薄膜上而形成第二主图案。 通过使用由不同钝化膜分离的多层主薄膜，可以重复地进行能够减小图案间距的间隔光刻，并且在形成微米尺度图案之后，图案间距重复减小而没有形状变形，从而形成纳米级精细图案 均匀地在广泛的地区。
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