公开(公告)号：US06171899B2

公开(公告)日：2001-01-09

申请号：US09267535

申请日：1999-03-12

Applicant: Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

Inventor： Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/76838

Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer. A photolithography and etching process is performed to remove a part of the second conductive layer. The second metal layer remaining on the inter-layer dielectric layer is used as a wiring line for interconnection. The glue layer remaining on the dielectric film is used as an upper electrode.

Abstract translation: 一种制造电容器的方法。 在所提供的基板上形成第一金属层。 在第一金属层上形成电介质膜。 电介质膜可以是单层结构或包括各种介电材料的多层结构。 进行快速热处理（RTP），例如快速热退火或等离子体处理，以提高电介质膜的质量。 进行光刻和蚀刻处理以去除电介质膜和第一金属层的一部分以暴露层间电介质层的一部分。 剩余的第一导电层用作下电极。 在暴露的层间电介质层和电介质膜上进行常规的互连工艺。 例如，在暴露的层间电介质层和电介质膜上形成胶层。 第二金属层形成在胶层上。 执行光刻和蚀刻工艺以去除第二导电层的一部分。 残留在层间电介质层上的第二金属层用作互连布线。 残留在电介质膜上的胶层用作上电极。

公开(公告)号：US5665995A

公开(公告)日：1997-09-09

申请号：US429603

申请日：1995-04-27

Applicant: Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

Inventor： Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/76

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

Abstract translation: 具有单元阵列的ROM器件具有形成在衬底中的导体。 形成绝缘体，平行导体与线区域正交形成，薄至约2000安。 在导体上形成厚度约为3000或更小的玻璃绝缘体被回流。 形成玻璃绝缘体上的触点和金属层。 抗蚀剂被图案化并用于蚀刻金属中的抗蚀剂图案。 在还原气体气氛中，通过在小于或等于约520℃退火器件使杂质离子激活之前，用厚度约为1000的层去除第二抗蚀剂和器件钝化。 抗蚀剂除去后，形成第二抗蚀剂并用定制的编码图案曝光以形成掩模。 离子以约1E14和3E14原子/ cm2的剂量注入到基底中，其能量小于或等于200keV，通过绝缘体中的开口与导体相邻。

公开(公告)号：US5576573A

公开(公告)日：1996-11-19

申请号：US454701

申请日：1995-05-31

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/112 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/112 ,  H01L29/42368 ,  Y10S438/981

Abstract: A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

Abstract translation: 一种用于掩模ROM器件的多状态存储单元。 源极/漏极区域沿着衬底和位线的平面上沿着第一方向延伸的条带布置在衬底上。 栅极氧化物层沿着第二方向布置在基板上。 栅极电极分别形成在每个栅极氧化物层的顶部上，作为沿第二方向延伸的条带。 栅极氧化物层具有多个选定的厚度，以差分系列排列。 每个晶体管沟道区以及它们相应的一个源极/漏极对，顶部的栅极氧化物层和进一步在其顶部的栅电极构成一个存储单元，其可以使其阈值电压在 差分系列的厚度允许存储用于存储器单元的多位等效的存储器内容。

公开(公告)号：US5504030A

公开(公告)日：1996-04-02

申请号：US505050

申请日：1995-07-21

Applicant: Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

Inventor： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

IPC: H01L21/8246

CPC classification number: H01L27/11246 ,  Y10S438/981

Abstract: A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells. The cross area of every two adjacent bit lines and one word line thereby forms a memory cell of the mask ROM wherein threshold voltages of the memory cells are altered proportional to the thicknesses of the gate oxide layer and the coding oxide layers.

Abstract translation: 一种制造掩模ROM器件的存储单元的方法。 沿着第一方向延伸的多个源极/漏极区域通过将杂质注入构成存储器单元的位线的半导体衬底中而形成。 在通过液相沉积工艺由阻挡层限定的半导体衬底的指定区域上形成编码氧化物层，由此通过反复进行液相沉积工艺以形成一系列 编码具有增加的厚度的氧化物层。 在不被编码氧化物层覆盖的半导体衬底的一部分上形成栅氧化层。 栅极氧化物层的厚度小于编码氧化物层的厚度。 通过在构成所述存储单元的字线的编码氧化物层和栅极氧化物层上沉积和图案化导电层来形成沿着与第一方向正交的第二方向延伸的多个栅电极。 因此，每两个相邻位线和一个字线的横截面形成掩模ROM的存储单元，其中存储单元的阈值电压与栅极氧化物层和编码氧化物层的厚度成比例地变化。

公开(公告)号：US20130113045A1

公开(公告)日：2013-05-09

申请号：US13290399

申请日：2011-11-07

Applicant: Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4966

Abstract: An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.

Abstract translation: 描述了静电放电（ESD）器件，包括栅极线，栅极线第一侧的源极区域，设置在栅极线的第二侧并具有梳齿部分的梳状漏极区域， 源极区域和漏极区域上的自对准硅化物层，以及源极区域和漏极区域上的自对准硅化物层上的接触塞。 每个梳齿部分在其顶端部分上具有至少一个接触塞。

公开(公告)号：US20120170160A1

公开(公告)日：2012-07-05

申请号：US12981521

申请日：2010-12-30

Applicant: Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H02H9/00

CPC classification number: H02H3/20 ,  H01L27/0262 ,  H01L2924/1301 ,  H01L2924/1304 ,  H02H9/04 ,  H02H9/046

Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

Abstract translation: ESD保护电路电连接在第一电力轨道和第二电力轨道之间，并且包括ESD保护装置，电连接在ESD保护装置和第一电力轨道之间的开关装置和电连接在第一电力轨道之间的低通滤波器 第一电力轨道和第一开关装置。 ESD保护器件包括BJT和电连接在BJT的基极和第一电源轨之间的第一电阻器。 当不发生ESD事件时，基极的电位大于或等于BJT发射极的电位。 当ESD事件发生时，基极的电位小于发射极的电位。

公开(公告)号：US07759957B2

公开(公告)日：2010-07-20

申请号：US11829104

申请日：2007-07-27

Applicant: Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

Inventor： Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

IPC: G01R31/02 ,  H01L21/66

CPC classification number: G01R31/2875 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a test structure, in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.

Abstract translation: 一种用于制造测试结构的方法，其中在晶片上形成加热板，用于加热位于加热板上方或附近的待测试结构。 加热板通过电连接到电流产生热量。 因此，加热板提供的热量和进入/待测结构的电输入/输出分开控制，彼此不相互影响。

公开(公告)号：US20090278170A1

公开(公告)日：2009-11-12

申请号：US12116231

申请日：2008-05-07

Applicant: Yun-Chi Yang ,  Jih-Shun Chiang ,  Cheng-Li Lin ,  Ju-Ping Chen ,  Kuan-Cheng Su

Inventor： Yun-Chi Yang ,  Jih-Shun Chiang ,  Cheng-Li Lin ,  Ju-Ping Chen ,  Kuan-Cheng Su

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/3148 ,  H01L29/456 ,  H01L29/665

Abstract: A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side of the gate structure, performing ant etching process to form recesses respectively in the source/drain, forming a barrier layer in the recesses; and performing a salicide process.

Abstract translation: 一种制造半导体器件的方法包括提供至少形成有栅极结构的衬底，分别在栅极结构的两侧在衬底中形成LDD，在栅极结构的侧壁形成间隔物，在栅极结构的侧壁形成源极/漏极 基板在栅极结构的两侧，进行蚂蚁蚀刻处理以分别在源极/漏极中形成凹槽，在凹部中形成阻挡层; 并执行自杀过程。

公开(公告)号：US5756376A

公开(公告)日：1998-05-26

申请号：US652895

申请日：1996-05-23

Applicant: Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

Inventor： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

IPC: H01L21/768 ,  H01L23/485 ,  H05K1/00 ,  H05K1/03

CPC classification number: H01L24/05 ,  H01L21/768 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L24/45 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14

Abstract: A method for removing a diffusion barrier layer on pad regions and diminishing the effect of plasma ions induced when removing a photoresist layer by a plasma asher. A two stage rapid thermal processing step is applied to the partially-removed diffusion barrier layer before a metal layer is formed. The first stage lasts a longer period of time at a lower temperature, for example, in the range of between 50 and 60 seconds at a temperature of about 600.degree. C. The second stage lasts a shorter period of time at a higher temperature, for example, in the range of between 20 and 30 seconds at a temperature of about 750.degree. C.

Abstract translation: 一种用于去除焊盘区域上的扩散阻挡层的方法，并且减少了通过等离子体灰化器去除光致抗蚀剂层时引起的等离子体离子的影响。 在形成金属层之前，将二阶段快速热处理步骤应用于部分去除的扩散阻挡层。 第一阶段在较低温度下持续更长的时间，例如在约600℃的温度下在50至60秒的范围内。第二阶段在较高温度下持续更短的时间段，对于 例如，在约750℃的温度下在20至30秒的范围内。

公开(公告)号：US5585297A

公开(公告)日：1996-12-17

申请号：US450298

申请日：1995-05-25

Applicant: Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

Inventor： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

IPC: H01L27/112 ,  H01L21/8246

CPC classification number: H01L27/112

Abstract: This is a method of manufacturing a multiple state MASK ROM semiconductor device on a P-type semiconductor substrate. The substrate includes an array of parallel buried bit lines oriented in a first direction. The process includes forming a gate oxide layer over the substrate including the buried bit lines; word lines over the gate oxide layer oriented orthogonally to the direction of the array of bit lines. Then form a first patterned implant mask over the device with a first set of openings through the mask. Ion implant dopant of a first dosage level through the openings in the mask to form implant doped regions of a first dosage level in the substrate. Form a second patterned implant mask over the device with a second set of openings through the mask. Then ion implant a dopant of a second dosage level through the openings in the mask to form implanted doped regions of a second dosage level in the substrate, the second dosage level being substantially different from the first dosage level.

Abstract translation: 这是在P型半导体衬底上制造多状态MASK ROM半导体器件的方法。 衬底包括沿第一方向定向的平行掩埋位线阵列。 该方法包括在包括掩埋位线的衬底上形成栅氧化层; 栅极氧化物层上的字线与位线阵列的方向正交定向。 然后在装置上形成第一图案化植入物掩模，其中第一组开口穿过掩模。 通过掩模中的开口具有第一剂量水平的离子注入掺杂剂，以在衬底中形成第一剂量水平的注入掺杂区域。 在设备上形成第二图案化植入物掩模，其中第二组开口穿过掩模。 然后通过掩模中的开口离子注入第二剂量水平的掺杂剂，以在底物中形成第二剂量水平的注入的掺杂区域，第二剂量水平基本上不同于第一剂量水平。