公开(公告)号：US07212143B1

公开(公告)日：2007-05-01

申请号：US11336657

申请日：2006-01-20

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi ,  Angelo Nagari

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi ,  Angelo Nagari

IPC: H03M1/12

CPC classification number: H03M1/1225

Abstract: A circuit for selectively converting at least one analog signal into corresponding digital codes. The circuit includes a management block having a plurality of inputs, each adapted for receiving a respective request signal carrying a request to convert the at least one analog signal. The management block is adapted to assign a priority level to the request signals based upon the input where the request signals are received, and is further operative to select one of the request signals based upon the assigned priority level and output a conversion start-up signal corresponding to the selected request signal. The circuit has a conversion block for receiving east one analog signal input and is connected to the management block to receive the conversion start-up signal as input, and start up conversion of the at least one analog signal.

Abstract translation: 用于选择性地将至少一个模拟信号转换成相应数字码的电路。 电路包括具有多个输入的管理块，每个输入适于接收携带转换所述至少一个模拟信号的请求的相应请求信号。 管理块适于基于接收到请求信号的输入来为请求信号分配优先级，并且还可操作以基于所分配的优先级来选择一个请求信号，并输出转换启动信号 对应于所选择的请求信号。 电路具有用于接收东一模拟信号输入的转换块，并连接到管理块以接收转换启动信号作为输入，并启动至少一个模拟信号的转换。

公开(公告)号：US07190300B2

公开(公告)日：2007-03-13

申请号：US11113954

申请日：2005-04-25

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno

IPC: H03M1/12

CPC classification number: G11C27/026 ,  G11C27/024 ,  H03H19/004 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/468

Abstract: A switched capacitance circuit including: a switched capacitance section, capable of receiving as input a signal and carrying out a sampling of said signal, the section comprising at least one group of capacitors each of which has a terminal connected to a common node; at least an operational stage including at least an input terminal connected to said common node, the operational stage providing a current to said common node for charging said group of capacitors during a sampling time interval of said signal. The circuit further includes an auxiliary circuit connected to said common node and capable of being activated/deactivated by an enabling signal for injecting a further current into said common node and increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.

Abstract translation: 一种开关电容电路，包括：开关电容部分，其能够接收信号并执行所述信号的采样，所述部分包括至少一组电容器，每个电容器的一组电容器具有连接到公共节点的端子; 至少包括连接到所述公共节点的输入端的操作级，所述操作级在所述信号的采样时间间隔期间向所述公共节点提供电流，以对所述电容器组进行充电。 该电路还包括连接到所述公共节点的辅助电路，并且能够通过用于将另外的电流注入到所述公共节点中的使能信号来激活/去激活，并且在至少等于一个等待时间间隔的至少一个时间间隔期间增加提供给所述公共节点的电流 所述采样间隔的分数。

公开(公告)号：US07106237B1

公开(公告)日：2006-09-12

申请号：US11097455

申请日：2005-04-01

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03M1/462

Abstract: The described converter comprises switched-capacitor quantization means for receiving an analog quantity to be converted, a register for a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means capable of responding to a conversion request signal by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register the digital quantity to be furnished as output. With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals emitted by the logic means. Also described is a method of using the converter that comprises the following phases: loading of the analog quantity in the quantization means, memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means.

Abstract translation: 所描述的转换器包括用于接收要转换的模拟量的开关电容量化装置，对应于模拟量的数字量的寄存器，定时脉冲发生器和能够通过激活量化装置来响应转换请求信号的逻辑装置 以这样的方式，它们将执行由定时脉冲定时的预定操作，并且将寄存器中的负载作为输出提供的数字量。 为了在转换期间节省电能并降低由发生器引起的噪声，发生器包括用于响应于由逻辑装置发出的调节信号而修改定时脉冲的持续时间和/或频率的装置。 还描述了一种使用该转​​换器的方法，该转换器包括以下阶段：在量化装置中加载模拟量，根据数字位的SAR技术在连续尝试过程中记录加载的模拟量和识别 对应于要转换的模拟量的代码。 响应于由逻辑装置发出的调节信号，定时脉冲的持续时间和/或频率在上述指示的至少一个期间被修改。

公开(公告)号：US20050231293A1

公开(公告)日：2005-10-20

申请号：US11055539

申请日：2005-02-09

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

IPC: H03B1/00 ,  H03H11/26 ,  H03K5/00 ,  H03K5/04 ,  H03K5/13

CPC classification number: H03H11/26 ,  H03K5/04 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00123 ,  H03K2005/00143 ,  H03K2005/00156 ,  H03K2005/00195

Abstract: The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.

Abstract translation: 电路包括第一环形振荡器，其包括奇数个反相元件，延迟元件和输出端子; 延迟元件相对于输入脉冲的预定边缘以相对于输入脉冲的另一边缘基本上没有时间延迟的预定时间延迟在其输入端响应脉冲。 为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括具有连接到第一振荡器的输出端的输出端的第二环形振荡器和具有连接到第一振荡器的输出端的双稳态逻辑电路， 连接到第一和第二振荡器的公共输出端的输出端子。 第一振荡器的反相元件和第二振荡器的反相元件中的至少一个的至少一个构成双稳态逻辑电路的一部分。

公开(公告)号：US06686865B2

公开(公告)日：2004-02-03

申请号：US10455894

申请日：2003-06-06

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

IPC: H03M112

CPC classification number: H03M1/68 ,  H03M1/468 ,  H03M1/804

Abstract: An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2p−1)·Cs−CATT=2p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.

Abstract translation: 模数转换器包括具有相应的二进制加权电容器的第一和第二阵列的第一和第二转换器段。 第一段的每个电容器具有连接到第一公共节点的第一电极和通过各个开关连接到第一参考电压端子和输入端子之一的第二电极。 第二段的每个电容器具有连接到第二公共节点的第一电极和通过相应开关连接到第一参考电压端子和输入端子之一的第二电极。 该转换器包括连接在第一和第二公共节点之间的耦合电容器和连接在第一公共节点和参考电压端子之间的电容装置。 耦合电容器和电容装置分别具有电容Cs和CATT，其基本上满足以下关系：（2

-1）.C-CATT = 2·C，其中p是在 第一转换器段，C为单位电容。

公开(公告)号：US09337829B2

公开(公告)日：2016-05-10

申请号：US14343099

申请日：2012-09-05

Applicant: Germano Nicollini ,  Marco Zamprogno

Inventor： Germano Nicollini ,  Marco Zamprogno

IPC: H03K3/01 ,  H03K17/687 ,  H03F1/52 ,  H03F3/185 ,  H03F3/30

CPC classification number: H03K17/6871 ,  H03F1/52 ,  H03F3/185 ,  H03F3/301

Abstract: An electronic USB or similar device 101 with a CMOS audio output stage 105 for driving, in a first mode, e.g., a headset via a port commonly used also in a second mode by a digital data transmission stage 103 for digital data and supply, the audio output stage P-channel transistor MP being switchably back-gate biased by a bias circuit 107 according to the operating mode to achieve high-voltage tolerance.

Abstract translation: 具有CMOS音频输出级105的电子USB或类似装置101，用于在第一模式中，例如通过数字数据传输级103用于数字数据和供应的第二模式中通常使用的端口驱动头戴式耳机， 根据操作模式，音频输出级P沟道晶体管MP由偏置电路107可切换地逆栅偏置以实现高电压容限。

公开(公告)号：US08947278B2

公开(公告)日：2015-02-03

申请号：US13822347

申请日：2011-09-08

Applicant: Germano Nicollini ,  Alberto Minuti ,  Marco Zamprogno

Inventor： Germano Nicollini ,  Alberto Minuti ,  Marco Zamprogno

IPC: H03M3/00 ,  H03M1/12 ,  G11C27/02 ,  H03F3/45

CPC classification number: H03M1/124 ,  G11C27/026 ,  H03F3/45475 ,  H03F3/45986 ,  H03F2203/45512 ,  H03F2203/45536

Abstract: A single-ended to differential buffer circuit is disclosed, adapted to couple at least an input analog signal to a receiving circuit. The buffer circuit comprises an output section comprising a differential amplifier having a first and a second input, a first and a second output. The buffer circuit further comprises an input section comprising a first and a second switched capacitor, each adapted to sample said input analog signal and having a first side and a second side, the first sides of the first and second switched capacitors being controllably connectable/disconnectable to/from said first and second outputs respectively. In the buffer circuit the second sides of said first and second switched capacitors are controllably connectable/disconnectable to/from said first and second inputs of the differential amplifier respectively. Moreover, in the buffer circuit the second sides of the first and second switched capacitors are controllably connectable/disconnectable to/from said second output and said first output respectively. A method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs is also disclosed.

Abstract translation: 公开了适用于将至少一个输入模拟信号耦合到接收电路的单端到差分缓冲电路。 缓冲电路包括输出部分，其包括具有第一和第二输入的差分放大器，第一和第二输出。 缓冲电路还包括一个输入部分，它包括一个第一和第二个开关电容器，每个开关电容器适于对所述输入模拟信号进行采样并具有第一侧和第二侧，第一和第二开关电容器的第一侧是可控地可连接/可断开的 分别来自所述第一和第二输出。 在缓冲电路中，所述第一和第二开关电容器的第二侧分别与差分放大器的第一和第二输入端分别可控地连接/断开。 此外，在缓冲电路中，第一和第二开关电容器的第二侧分别可控地与所述第二输出端和所述第一输出端连接/断开。 还公开了一种用于将至少单端输入模拟信号耦合到具有差分输入的接收电路的方法。

公开(公告)号：US20110095610A1

公开(公告)日：2011-04-28

申请号：US12893848

申请日：2010-09-29

Applicant: Pierangelo CONFALONIERI ,  Federico GUANZIROLI ,  Marco ZAMPROGNO

Inventor： Pierangelo CONFALONIERI ,  Federico GUANZIROLI ,  Marco ZAMPROGNO

IPC: H02J3/00

CPC classification number: H03K17/162 ,  H03M1/0845 ,  H03M1/12 ,  H03M1/66 ,  Y10T307/50

Abstract: A system includes analog supply circuitry providing first and second analog potentials. A switch module assumes first or second states to enable and inhibit transfer of an analog electrical signal from a source module to a user module based upon a driving electrical signal. A driving device drives, based upon the driving electrical signal, a control terminal of the switch module, allowing the switch module to assume the first or second state. The driving device allows the switch module to make a first driving transition from the first state to the second state, and a second driving transition from the second state to the first state. The driving device alternately connects the control terminal to a first reference potential, during the first state, and to a second reference potential, during the second state. The driving device connects the control terminal of the switch module to a third reference potential electrically distinct from the first and the second analog potentials, during each of the time intervals associated to the first or second driving transitions of the switch module.

Abstract translation: 系统包括提供第一和第二模拟电位的模拟电源电路。 开关模块基于驱动电信号，假设第一或第二状态来启用和禁止模拟电信号从源模块传送到用户模块。 驱动装置基于驱动电信号驱动开关模块的控制端子，允许开关模块呈现第一或第二状态。 驱动装置允许开关模块进行从第一状态到第二状态的第一驱动转变，以及从第二状态到第一状态的第二驱动转变。 在第二状态期间，驱动装置在第一状态期间交替地将控制端子连接到第一参考电位，并将第二参考电位交替地连接到第二参考电位。 在与开关模块的第一或第二驱动转换相关联的每个时间间隔期间，驱动装置将开关模块的控制端子连接到与第一和第二模拟电位电不同的第三参考电位。

公开(公告)号：US07742893B2

公开(公告)日：2010-06-22

申请号：US12035308

申请日：2008-02-21

Applicant: Pierangelo Confalonieri ,  Riccardo Martignone ,  Marco Zamprogno

Inventor： Pierangelo Confalonieri ,  Riccardo Martignone ,  Marco Zamprogno

IPC: G01R35/00

CPC classification number: H03H1/02 ,  H03H7/0153 ,  H03H2210/021 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2210/043

Abstract: A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop. The calibration circuit includes: a controllable capacitance unit suitable to receive a control signal and including at least one array of switched capacitors that can be activated by the control signal, the unit being such as to output a first signal characterized by a parameter depending on the amount of capacitance of the array activated by the control signal; a comparison unit suitable to receive the first signal to assess whether the parameter meets a preset condition and to output a comparison signal representative of the assessment result; a control and timing logic unit suitable to receive the comparison signal to change this control signal based on the comparison signal, characterized in that the first signal is a logic signal and the parameter is a time parameter of the first signal.

Abstract translation: 校准电路根据可调电容校准具有时间常数的电路的可调电容。 校准电路输出一个载有用于校准电容器的信息的校准信号，并包括校准环路。 所述校准电路包括：可控电容单元，其适于接收控制信号并且包括可被所述控制信号激活的至少一个开关电容阵列，所述单元使得输出第一信号，所述第一信号的特征在于根据 由控制信号激活的阵列的电容量; 适于接收第一信号以评估参数是否满足预置条件并输出表示评估结果的比较信号的比较单元; 适于接收比较信号以根据比较信号改变该控制信号的控制和定时逻辑单元，其特征在于，第一信号是逻辑信号，该参数是第一信号的时间参数。

公开(公告)号：US20100123612A1

公开(公告)日：2010-05-20

申请号：US12622166

申请日：2009-11-19

Applicant: Marco Zamprogno ,  Federico Guanziroli ,  Germano Nicollini ,  Pierangelo Confalonieri

Inventor： Marco Zamprogno ,  Federico Guanziroli ,  Germano Nicollini ,  Pierangelo Confalonieri

IPC: H03M1/34

CPC classification number: H03F3/505 ,  H03F2200/375 ,  H03F2200/447 ,  H03F2200/453 ,  H03F2203/5031 ,  H03M1/089 ,  H03M1/12

Abstract: An analog-to-digital conversion circuit and device having an input stage arranged to receive an input signal and to provide an output analog signal as a function of the input signal; an analog-to-digital conversion block arranged to receive the output analog signal and to provide a respective output digital signal. The input stage includes a first voltage buffer arranged to provide the output analog signal to the conversion block as the translation of the input signal of an amount equal to a translation voltage; a second voltage buffer arranged to provide a first reference signal to the conversion block that is representative of the translation of a first reference voltage of an amount equal to the translation voltage, so that the conversion block stores the input signal as the difference of the input signal and the first reference voltage regardless of the translation voltage.

Abstract translation: 一种具有输入级的模拟 - 数字转换电路和器件，其被布置成接收输入信号并提供作为输入信号的函数的输出模拟信号; 一个模拟 - 数字转换块，用于接收输出模拟信号并提供相应的输出数字信号。 输入级包括第一电压缓冲器，其布置成将输出模拟信号提供给转换块，作为等于平移电压的量的输入信号的转换; 第二电压缓冲器，其被布置为向所述转换块提供表示等于所述平移电压的量的第一参考电压的转换的第一参考信号，使得所述转换块将所述输入信号存储为所述输入的差 信号和第一个参考电压，无论平移电压如何。