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    Through-circuit Vias in interconnect structures
    23.
    发明授权
    Through-circuit Vias in interconnect structures 有权

    公开(公告)号：US12293959B2

    公开(公告)日：2025-05-06

    申请号：US18232200

    申请日：2023-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jian-Hong Lin ,  Hsin-Chun Chang ,  Ming-Hong Hsieh ,  Ming-Yih Wang ,  Yinlung Lu

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

    Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

    Semiconductor device with self-aligned vias
    24.
    发明授权
    Semiconductor device with self-aligned vias 有权

    公开(公告)号：US12293944B2

    公开(公告)日：2025-05-06

    申请号：US17750887

    申请日：2022-05-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Han Chen ,  Chien-Chih Chiu ,  Ming-Chung Liang

    IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532

    Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

    Contacts for Semiconductor Devices and Methods of Forming the Same
    26.
    发明申请
    Contacts for Semiconductor Devices and Methods of Forming the Same 有权

    公开(公告)号：US20250142932A1

    公开(公告)日：2025-05-01

    申请号：US19009221

    申请日：2025-01-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H10D64/23 ,  H10D30/01 ,  H10D62/17 ,  H10D64/01 ,  H10D64/27 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83 ,  H10D84/85

    Abstract: Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.

    Lithography system and methods
    30.
    发明授权
    Lithography system and methods 有权

    公开(公告)号：US12287572B2

    公开(公告)日：2025-04-29

    申请号：US17232483

    申请日：2021-04-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng Hung Tsai ,  Sheng-Kang Yu ,  Shang-Chieh Chien ,  Heng-Hsin Liu ,  Li-Jui Chen

    IPC: G03F7/00 ,  G03F7/20 ,  G03F7/22 ,  G03F7/36

    Abstract: A method includes: depositing a mask layer over a substrate; directing first radiation reflected from a central collector section of a sectional collector of a lithography system toward the mask layer according to a pattern; directing second radiation reflected from a peripheral collector section of the sectional collector toward the mask layer according to the pattern, wherein the peripheral collector section is vertically separated from the central collector section by a gap; forming openings in the mask layer by removing first regions of the mask layer exposed to the first radiation and second regions of the mask layer exposed to the second radiation; and removing material of a layer underlying the mask layer exposed by the openings.

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