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    Impedance control using fuses
    21.
    发明授权
    Impedance control using fuses 有权
    使用熔断器进行阻抗控制

    公开(公告)号：US06243283B1

    公开(公告)日：2001-06-05

    申请号：US09589922

    申请日：2000-06-07

    Applicant: Claude Louis Bertin ,  John A. Fifield ,  Erik Leigh Hedberg ,  Russell J. Houghton ,  Timothy Dooling Sullivan ,  Steven William Tomashot ,  William Robert Tonti

    Inventor： Claude Louis Bertin ,  John A. Fifield ,  Erik Leigh Hedberg ,  Russell J. Houghton ,  Timothy Dooling Sullivan ,  Steven William Tomashot ,  William Robert Tonti

    IPC: G11C506

    CPC classification number: H01L23/481 ,  G11C17/16 ,  H01L25/0657 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2224/4826 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.

    Abstract translation: 一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。 该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载 在I / O连接。 这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置 的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。 堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

    Chip thermal protection device
    22.
    发明授权
    Chip thermal protection device 有权
    芯片热保护装置

    公开(公告)号：US06219215B1

    公开(公告)日：2001-04-17

    申请号：US09303042

    申请日：1999-04-30

    Applicant: Claude Louis Bertin ,  Erik Leigh Hedberg ,  Timothy Dooling Sullivan ,  William Robert Tonti

    Inventor： Claude Louis Bertin ,  Erik Leigh Hedberg ,  Timothy Dooling Sullivan ,  William Robert Tonti

    IPC: H02H300

    CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  Y10T307/25 ,  H01L2924/00

    Abstract: A gap conducting structure for an integrated electronic circuit that functions as an electronic fuse device and that is integrated as part of the semi-conductor chip wiring for providing over-current and thermal runaway protection. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to destruct a part of the partially exposed/fully exposed conducting line, thus preventing thermal runaway and over-current condition. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer.

    Abstract translation: 用作集成电子电路的间隙导电结构，其用作电子熔断器件，并且被集成为用于提供过电流和热失控保护的半导体芯片布线的一部分。 间隙导电结构包括一个或多个预定体积的气隙区域，其完全或部分地暴露IC中的层间导体层的长度。 或者，气隙区域可以完全位于相应导体下方的电介质区域内并被绝缘体分隔开。 当用作熔丝时，间隙区域用于降低远离导体的暴露部分的热导率，使得能够以较低的施加电压在导电线中产生更高的热流，足以破坏部分暴露/完全暴露的导电线的一部分 ，从而防止热失控和过电流状态。 间隙的存在以及保险丝的存在是可扩展的，并且可以根据电路设计者定义的保险丝的特性来适应其必须携带的电流的容量。

    Impedance control using fuses
    23.
    发明授权
    Impedance control using fuses 有权
    使用熔断器进行阻抗控制

    公开(公告)号：US6141245A

    公开(公告)日：2000-10-31

    申请号：US302902

    申请日：1999-04-30

    Applicant: Claude Louis Bertin ,  John A. Fifield ,  Erik Leigh Hedberg ,  Russell J. Houghton ,  Timothy Dooling Sullivan ,  Steven William Tomashot ,  William Robert Tonti

    Inventor： Claude Louis Bertin ,  John A. Fifield ,  Erik Leigh Hedberg ,  Russell J. Houghton ,  Timothy Dooling Sullivan ,  Steven William Tomashot ,  William Robert Tonti

    IPC: H01L27/02 ,  G11C17/16 ,  H01L25/065 ,  G11C16/04

    CPC classification number: H01L23/481 ,  G11C17/16 ,  H01L25/0657 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2224/4826 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3011

    Abstract: A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.

    Abstract translation: 一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。 该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载 在I / O连接。 这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置 的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。 堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

    Optically transparent wires for secure circuits and methods of making same
    25.
    发明授权
    Optically transparent wires for secure circuits and methods of making same 有权
    用于安全电路的光学透明导线及其制造方法

    公开(公告)号：US08017514B2

    公开(公告)日：2011-09-13

    申请号：US12115056

    申请日：2008-05-05

    Applicant: Stephen Peter Ayotte ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Kimball M. Watson

    Inventor： Stephen Peter Ayotte ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Kimball M. Watson

    IPC: H01L21/00

    CPC classification number: H01L23/522 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/57 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

    Abstract translation: 一种结构和方法。 该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测 通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

    OPTOELECTRONIC MEMORY DEVICES
    27.
    发明申请
    OPTOELECTRONIC MEMORY DEVICES 有权
    光电存储器件

    公开(公告)号：US20100290264A1

    公开(公告)日：2010-11-18

    申请号：US12842158

    申请日：2010-07-23

    Applicant: Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

    Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

    IPC: G11C13/04 ,  G11C11/00

    CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

    Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.

    Abstract translation: 一个结构。 该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。 电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。 电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

    Through-wafer vias
    29.
    发明授权
    Through-wafer vias 有权
    通晶圆通孔

    公开(公告)号：US07741722B2

    公开(公告)日：2010-06-22

    申请号：US11690181

    申请日：2007-03-23

    Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

    Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

    Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

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