公开(公告)号：US20170352531A1

公开(公告)日：2017-12-07

申请号：US15684827

申请日：2017-08-23

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Schubert S. CHU ,  Jessica S. KACHIAN ,  David THOMPSON ,  Jeffrey ANTHIS

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/04 ,  H01L21/283 ,  H01J37/32

CPC classification number: H01L21/0228 ,  C23C16/04 ,  C23C16/45544 ,  C23C16/52 ,  H01J37/32009 ,  H01J37/32357 ,  H01J37/32522 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02049 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/67745

Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.

公开(公告)号：US20160126093A1

公开(公告)日：2016-05-05

申请号：US14870792

申请日：2015-09-30

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Hua CHUNG ,  Jenn-Yue WANG ,  Xuebin LI ,  Yi-Chiau HUANG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/7848 ,  H01L29/7851

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract translation: 本公开的实施方式一般涉及在外延膜上硅材料外延生长的方法。 在一个实施方案中，该方法包括在半导体鳍片上形成外延膜，其中外延膜包括具有第一面和第二面的顶表面，并且通过交替地在至少外延膜的顶表面上形成外延层 将顶表面暴露于包含一种或多种硅烷的第一前体气体和包含一种或多种氯化硅烷的第二前体气体，其温度为约375℃至约450℃，室压力为约5托至约 20乇

公开(公告)号：US20250132154A1

公开(公告)日：2025-04-24

申请号：US18491584

申请日：2023-10-20

Applicant: Applied Materials, Inc.

Inventor： Chen-Ying WU ,  Abhishek DUBE ,  Zuoming ZHU

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/52 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor processing methods for anisotropic film growth. The method includes heating a substrate positioned in a processing chamber. The method includes flowing one or more process gases over the substrate. The one or more process gases include trichlorosilane (TCS) and hydrochloric acid. The method includes depositing one or more layers on one or more fins on the substrate. The deposition of the one or more layers includes forming the one or more layers at a first growth rate along a first dimension and a second growth rate along a second dimension, and the second growth rate is faster than the first growth rate.

公开(公告)号：US20250037997A1

公开(公告)日：2025-01-30

申请号：US18781631

申请日：2024-07-23

Applicant: Applied Materials, Inc.

Inventor： Ruiying HAO ,  Thomas John KIRSCHENHEITER ,  Fredrick FISHBURN ,  Abhishek DUBE ,  Raghuveer S. MAKALA ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L21/02 ,  H01L21/306

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. One or more groups of layers are formed on top of the substrate. A compensation layer is formed on top of at least one group of layers. At least one silicon layer is formed on top of the compensation layer. At least a portion of one or more layers in the one or more groups of layers is etched. The semiconductor device is formed.

公开(公告)号：US20220322492A1

公开(公告)日：2022-10-06

申请号：US17223940

申请日：2021-04-06

Applicant: Applied Materials, Inc.

Inventor： Shu-Kwan LAU ,  Brian Hayes BURROWS ,  Zhiyuan YE ,  Richard O. COLLINS ,  Enle CHOO ,  Danny D. WANG ,  Shainish NELLIKKA ,  Toshiyuki NAKAGAWA ,  Abhishek DUBE ,  Ala MORADIAN ,  Kartik Bhupendra SHAH

IPC: H05B3/00

Abstract: A process chamber includes a chamber body having a ceiling disposed above a floor with a chassis and an injector ring disposed therebetween. Upper and lower clamp rings secure the upper and floors, respectively, in place. An upper heating module is coupled to the upper clamp ring above the ceiling. A lower heating module is coupled to the lower clamp ring below the floor.

公开(公告)号：US20200258997A1

公开(公告)日：2020-08-13

申请号：US16773848

申请日：2020-01-27

Applicant: Applied Materials, Inc.

Inventor： Gaurav THAREJA ,  Xuebin LI ,  Abhishek DUBE ,  Yi-Chiau HUANG ,  Andy LO ,  Patricia M. LIU ,  Sanjay NATARAJAN ,  Saurabh CHOPRA

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40

Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

公开(公告)号：US20190301011A1

公开(公告)日：2019-10-03

申请号：US16366570

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： Geetika BAJAJ ,  Prerna Sonthalia GORADIA ,  Robert Jan VISSER ,  Abhishek DUBE ,  Flora Fong-Song CHANG ,  Hua CHUNG

IPC: C23C16/44 ,  C23C16/52 ,  C23C16/48

Abstract: Embodiments of the disclosure may provide a method and apparatus for cleaning an epi-chamber at a low temperature so that residues are quickly eliminated from a surface of the epi-chamber after a performing a low temperature epitaxial deposition process. Some of the benefits of the present disclosure include flowing a chlorine containing gas to an improved epi-chamber having UV capability to chlorinate and quickly remove the epitaxial deposition residues at a low cleaning process temperature. As such, residues are decreased or removed from the epi-chamber such that further processing may be performed.

公开(公告)号：US20180230624A1

公开(公告)日：2018-08-16

申请号：US15889669

申请日：2018-02-06

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Xuebin LI ,  Hua CHUNG ,  Flora Fong-Song CHANG

IPC: C30B25/18 ,  C30B29/06 ,  C30B33/12 ,  C23C16/02 ,  C23C16/56 ,  H01L21/67 ,  H01L21/02 ,  H01L21/3065

Abstract: The present disclosure generally relate to a cluster tool and methods for forming an epitaxial layer on a semiconductor device. In one implementation, the cluster tool includes a transfer chamber, a pre-clean chamber coupled to the transfer chamber, a plasma-cleaning chamber coupled to the transfer chamber, a deposition chamber coupled to the transfer chamber, an etch chamber coupled to the transfer chamber, and a thermal process chamber coupled to the transfer chamber.

公开(公告)号：US20170323795A1

公开(公告)日：2017-11-09

申请号：US15585016

申请日：2017-05-02

Applicant: Applied Materials, Inc.

Inventor： Xuebin LI ,  Hua CHUNG ,  Flora Fong-Song CHANG ,  Abhishek DUBE ,  Yi-Chiau HUANG ,  Schubert S. CHU

IPC: H01L21/3065 ,  H01L29/66 ,  H01L29/08 ,  H01L21/67

CPC classification number: H01L21/3065 ,  H01L21/67069 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836 ,  H01L29/7848

Abstract: Methods for forming transistors are provided. A substrate is placed in a processing chamber, and a plurality of epitaxial features is formed on the substrate. The epitaxial feature has at least a surface having the (110) plane and a surface having the (100) plane. An etchant or a gas mixture including an etchant and an etch enhancer or an etch suppressor is introduced into the processing chamber to remove a portion of the epitaxial feature. Etch selectivity between the surface having the (110) plane and the surface having the (100) plane can be tuned by varying the pressure within the processing chamber, the ratio of the flow rate of the etchant or gas mixture to the flow rate of a carrier gas, and/or the ratio of the flow rate of the etch enhancer or suppressor to the flow rate of the etchant.

公开(公告)号：US20170084449A1

公开(公告)日：2017-03-23

申请号：US15247586

申请日：2016-08-25

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Schubert S. CHU ,  Jessica S. KACHIAN ,  David THOMPSON ,  Jeffrey ANTHIS

IPC: H01L21/02 ,  H01J37/32 ,  C23C16/455 ,  H01L21/283

CPC classification number: H01L21/0228 ,  C23C16/04 ,  C23C16/45544 ,  H01J37/32009 ,  H01J37/32357 ,  H01J37/32522 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02049 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/67745

Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.