公开(公告)号：US09911702B2

公开(公告)日：2018-03-06

申请号：US14268981

申请日：2014-05-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

公开(公告)号：US08686568B2

公开(公告)日：2014-04-01

申请号：US13629397

申请日：2012-09-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

Abstract translation: 封装衬底包括芯，多个第一电路段和多个导电柱。 每个第一电路段具有设置在芯上的图案化金属层，设置在图案化金属层上的阻挡层和设置在阻挡层上的上部金属图案。 导电柱穿透芯，图案化金属层和阻挡层，并接触上部金属图案。 导电柱由可以选择性地去除而不影响阻挡层的材料形成。

公开(公告)号：US20140084480A1

公开(公告)日：2014-03-27

申请号：US13629397

申请日：2012-09-27

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

Abstract translation: 封装衬底包括芯，多个第一电路段和多个导电柱。 每个第一电路段具有设置在芯上的图案化金属层，设置在图案化金属层上的阻挡层和设置在阻挡层上的上部金属图案。 导电柱穿透芯，图案化金属层和阻挡层，并接触上部金属图案。 导电柱由可以选择性地去除而不影响阻挡层的材料形成。

公开(公告)号：US20140008814A1

公开(公告)日：2014-01-09

申请号：US13895704

申请日：2013-05-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并从上电路层向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。

公开(公告)号：US10446411B2

公开(公告)日：2019-10-15

申请号：US16102527

申请日：2018-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Yu-Tzu Peng

IPC: H01L23/48 ,  H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31 ,  H05K1/14 ,  H05K3/28 ,  H01L23/538

Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

公开(公告)号：US10103110B2

公开(公告)日：2018-10-16

申请号：US15873784

申请日：2018-01-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

公开(公告)号：US20160284659A1

公开(公告)日：2016-09-29

申请号：US14667317

申请日：2015-03-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee

IPC: H01L23/00 ,  H05K1/11 ,  H05K3/10 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3157 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48245 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/1511 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/10 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.

Abstract translation: 本公开涉及一种半导体衬底结构，半导体封装及其制造方法。 半导体衬底结构包括导电结构和电介质结构。 导电结构具有与第一导电表面相对的第一导电表面和第二导电表面。 电介质结构覆盖导电结构的至少一部分，并且具有与第一电介质表面相对的第一电介质表面和第二电介质表面。 第一导电表面不从第一电介质表面突出，并且第二导电表面从第二电介质表面凹陷。 电介质结构包括或由感光树脂形成，并且电介质结构在第二电介质表面中限定电介质开口以暴露第二导电表面的一部分。

公开(公告)号：US20160104667A1

公开(公告)日：2016-04-14

申请号：US14971165

申请日：2015-12-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L23/498 ,  H01L21/027 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

公开(公告)号：US08884443B2

公开(公告)日：2014-11-11

申请号：US13895704

申请日：2013-05-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L21/48 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并从上电路层向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。

公开(公告)号：US20140308778A1

公开(公告)日：2014-10-16

申请号：US14313046

申请日：2014-06-24

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Hsiang-Ming Feng ,  Bing-Yun Cheng

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract translation: 制造半导体器件封装的方法的实施例包括散热器矩阵和衬底。 多个半导体器件附接到基板。 然后，在散热片基板和基板之间形成封装体，其中封装体封装半导体器件。 然后，形成多个第一切割槽，其中第一切割槽延伸穿过散热器矩阵并且部分地延伸到包装主体中。 然后，形成多个第二切割槽，其中第二切割槽延伸穿过基板并通过封装主体延伸到第一切割槽，从而将散热器矩阵和基板分离成多个单独的半导体器件封装。