公开(公告)号：US09490214B2

公开(公告)日：2016-11-08

申请号：US14845435

申请日：2015-09-04

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC classification number: H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

公开(公告)号：US09166011B2

公开(公告)日：2015-10-20

申请号：US14328247

申请日：2014-07-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seong Il Kim ,  Dong Min Kang ,  Sang Heung Lee ,  Ho Kyun Ahn ,  Hyung Sup Yoon ,  Byoung Gue Min ,  Jong Won Lim

IPC: H01L21/338 ,  H01L29/423 ,  H01L29/778 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L29/42312 ,  H01L21/28114 ,  H01L21/28587 ,  H01L21/28593 ,  H01L29/42316 ,  H01L29/66863 ,  H01L29/778 ,  H01L29/812

Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 μm or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.

Abstract translation: 公开了一种具有稳定的栅极结构的半导体器件及其制造方法，其中通过在栅极头的宽度方向上的栅极头附近还包括多个栅极脚来稳定栅极结构，以作为支撑体 在包括具有0.2μm或更小的长度的精细栅极脚的栅极结构中，并且栅极头具有预定尺寸。 因此，可以防止半导体器件的栅电极塌陷，并且在半导体器件的处理期间或之后提高半导体器件的可靠性。

公开(公告)号：US09159612B2

公开(公告)日：2015-10-13

申请号：US14021269

申请日：2013-09-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC classification number: H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。

公开(公告)号：US09012920B2

公开(公告)日：2015-04-21

申请号：US13867328

申请日：2013-04-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chull Won Ju ,  Hae Cheon Kim ,  Hyung Sup Yoon ,  Woo Jin Chang ,  Sang-Heung Lee ,  Dong-Young Kim ,  Jong-Won Lim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong Min Lee ,  Eun Soo Nam

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L23/00

CPC classification number: H01L29/2003 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L29/41758 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014

Abstract: Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded. By this configuration, it is possible to reduce the process costs by forming the bump on the substrate based on the wafer level, rapidly emit the heat generated from an AlGaN HEMT device by forming the sub source contact pad and the sub drain contact pad of the substrate in the active region, and efficiently emit the heat generated from the AlGaN HEMT device by forming a via hole on the substrate and filling the via hole with the conductive metal.

Abstract translation: 公开了一种GaN（氮化镓）复合功率半导体器件及其制造方法。 氮化镓化合物功率半导体器件包括：通过在晶片上生长形成的氮化镓复合元素; 包括源极，漏极和与氮化镓复合元件连接的栅极的接触焊盘; 将氮化镓化合物元件倒装芯片接合的模块基板; 形成在所述模块基板上的焊盘; 以及形成在模块基板的焊盘上的凸点，使得接触焊盘和焊盘被倒装芯片接合。 通过这种结构，可以通过基于晶片级在基板上形成凸块来降低处理成本，通过形成子源接触焊盘和子漏极接触焊盘，快速地发射由AlGaN HEMT器件产生的热量 衬底，并且通过在衬底上形成通孔并用导电金属填充通孔，从而有效地发射由AlGaN HEMT器件产生的热量。

公开(公告)号：US08841969B2

公开(公告)日：2014-09-23

申请号：US13670016

申请日：2012-11-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang-Heung Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Chull Won Ju ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H03G3/12

CPC classification number: H03G1/0082 ,  H03G1/0088 ,  H03G3/3084

Abstract: Disclosed is an automatic gain control feedback amplifier that can arbitrarily control a gain even when a difference in input signal is large. The automatic gain control feedback amplifier includes: an amplification circuit unit configured to amplify voltage input from an input terminal and output the amplified voltage to an output terminal; a feedback circuit unit connected between the input terminal and the output terminal and including a feedback resistor unit of which a total resistance value is determined by one or more control signals and a feedback transistor connected to the feedback resistor unit in parallel; and a bias circuit unit configured to supply predetermined bias voltage to the feedback transistor.

Abstract translation: 公开了一种自动增益控制反馈放大器，其即使当输入信号的差异大时也可以任意地控制增益。 自动增益控制反馈放大器包括：放大电路单元，被配置为放大从输入端输入的电压，并将放大的电压输出到输出端; 连接在输入端子和输出端子之间的反馈电路单元，包括反馈电阻器单元，其总电阻值由一个或多个控制信号确定，反馈晶体管并联连接到反馈电阻器单元; 以及偏置电路单元，被配置为向所述反馈晶体管提供预定的偏置电压。

公开(公告)号：US20140160689A1

公开(公告)日：2014-06-12

申请号：US13959666

申请日：2013-08-05

Applicant: Electronics and Telecommunications Research Institute

Inventor： Dong Min KANG ,  Chull Won Ju ,  Seong-Il Kim ,  Sang-Heung Lee ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H05K1/02

CPC classification number: H01L23/66 ,  H01L23/49844 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package includes a ground plate, a chip mounting plate disposed at a side of the ground plate and having a top surface lower than a top surface of the ground plate, a chip on the chip mounting plate, a first input/output terminal opposite to the chip mounting plate and disposed at another side of the ground plate, and a second input/output terminal opposite to the ground plate and disposed at a side of the chip mounting plate. The first and second input/output terminals are electrically connected to the chip.

Abstract translation: 一种封装，包括接地板，设置在接地板一侧的芯片安装板，具有比接地板的顶表面低的顶表面，芯片安装板上的芯片，与第一输入/输出端子相对的第一输入/输出端子 芯片安装板并且设置在接地板的另一侧，以及与接地板相对的第二输入/输出端子，并且设置在芯片安装板的一侧。 第一和第二输入/输出端子与芯片电连接。

公开(公告)号：US20130207730A1

公开(公告)日：2013-08-15

申请号：US13743667

申请日：2013-01-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jongmin LEE ,  Byoung-Gue Min ,  Seong-Il Kim ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H03H7/38 ,  H01G7/00 ,  H03F3/21

CPC classification number: H01L21/8222 ,  H01G7/00 ,  H01L27/0647 ,  H01L27/0658 ,  H01L29/93 ,  H03F1/565 ,  H03F3/21 ,  H03F2200/36 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2200/391 ,  H03H7/38 ,  Y10T29/43

Abstract: Disclosed is an impedance matching circuit capable of wideband matching. The impedance matching circuit includes: a first variable inductor unit of which one end is connected to the first node and an inductance value varies; a second inductor unit connected between the first node and a second node and having a variable inductance value; a first variable capacitor unit of which one end is connected to the first node and a capacitance value varies; and a second variable capacitor unit of which one end is connected to the second node and a capacitance value varies, and the other end of the first variable capacitor unit and the other end of the second variable capacitor unit are connected to a ground voltage terminal to perform the impedance matching between a circuit connected to the other end of the first variable inductor unit and a circuit connected to the second node.

Abstract translation: 公开了能够进行宽带匹配的阻抗匹配电路。 阻抗匹配电路包括：第一可变电感器单元，其一端连接到第一节点，电感值变化; 连接在第一节点和第二节点之间并具有可变电感值的第二电感器单元; 第一可变电容器单元，其一端连接到第一节点，电容值变化; 以及第二可变电容器单元，其一端连接到第二节点并且电容值变化，并且第一可变电容器单元的另一端和第二可变电容器单元的另一端连接到接地电压端子 执行连接到第一可变电感器单元的另一端的电路与连接到第二节点的电路之间的阻抗匹配。