公开(公告)号：US08817530B2

公开(公告)日：2014-08-26

申请号：US13657002

申请日：2012-10-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C7/10 ,  G11C7/00 ,  G11C7/12 ,  G11C11/00 ,  G11C11/16 ,  G11C11/02 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1084 ,  G11C7/12 ,  G11C11/00 ,  G11C11/02 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/50008

Abstract: An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array, and the data stored in the latch determines whether to selectively enable the sense amplifier.

Abstract translation: 模拟读取电路测量电阻存储元件阵列中的多个位中的每一个的电阻。 存储在锁存器内的数据确定是否选择使能模拟读取电路。 在替代实施例中，读出放大器耦合到锁存器和阵列，并且存储在锁存器中的数据确定是否选择性地使能读出放大器。

公开(公告)号：US20140230079A1

公开(公告)日：2014-08-14

申请号：US14175063

申请日：2014-02-07

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F21/78

CPC classification number: G06F21/79 ,  G06F3/062 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/78 ,  G06F21/86 ,  G06F2221/2143 ,  G11C7/24 ,  G11C11/1695

Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

Abstract translation: 响应于篡改尝试指示，存储器设备选择性地禁用一个或多个存储器操作。 禁用可以通过不同的技术实现，包括改变与执行存储器操作相关联的偏置电压，选通执行存储器操作所需的电流，以及将所需电流限制在低于操作所需阈值幅度的幅度。 禁用内存操作后，可以生成模拟电流。 模拟电流旨在模拟在不被禁用时在存储器操作期间通常消耗的电流，从而导致用户认为即使正在尝试的存储器操作实际上不被执行，设备也继续正常地操作。

公开(公告)号：US11335728B2

公开(公告)日：2022-05-17

申请号：US16881958

申请日：2020-05-22

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Thomas Andre ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US11127896B2

公开(公告)日：2021-09-21

申请号：US16251230

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Frederick Mancoff ,  Sumio Ikegawa

IPC: H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.

公开(公告)号：US10700123B2

公开(公告)日：2020-06-30

申请号：US16143088

申请日：2018-09-26

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US10658013B2

公开(公告)日：2020-05-19

申请号：US16252067

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Frederick Neumeyer

IPC: G11C5/14 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22 ,  G11C29/02 ,  G11C29/50

Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.

公开(公告)号：US10395699B2

公开(公告)日：2019-08-27

申请号：US14496984

申请日：2014-09-25

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C7/12 ,  G11C7/06 ,  G11C5/06

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

公开(公告)号：US20190147971A1

公开(公告)日：2019-05-16

申请号：US16242892

申请日：2019-01-08

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G11C29/50 ,  G06F11/10 ,  G06F11/08 ,  G11C11/16

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US20180267899A1

公开(公告)日：2018-09-20

申请号：US15986167

申请日：2018-05-22

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian ,  Javed S. Barkatullah

IPC: G06F12/0893 ,  G06F3/06 ,  G11C7/10 ,  G06F12/0802 ,  G11C11/16 ,  G11C16/32 ,  G11C7/22 ,  G06F12/0862

CPC classification number: G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0215 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2024 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272 ,  Y02D10/13

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US09711566B1

公开(公告)日：2017-07-18

申请号：US15230402

申请日：2016-08-06

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.