公开(公告)号：US20230309416A1

公开(公告)日：2023-09-28

申请号：US18123729

申请日：2023-03-20

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Han Kyu Lee ,  Sanjeev AGGARWAL ,  Jijun SUN ,  Syed M. ALAM ,  Tom ANDRE

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  H10B61/22 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US20230297283A1

公开(公告)日：2023-09-21

申请号：US17884040

申请日：2022-08-09

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Iftekhar RAHMAN ,  Pedro SANCHEZ

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0652 ,  G06F3/0604 ,  G06F3/0673

Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.

公开(公告)号：US20230230623A1

公开(公告)日：2023-07-20

申请号：US18189590

申请日：2023-03-24

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C7/1069 ,  G11C5/146 ,  G11C7/1045 ,  G11C7/1096

Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

公开(公告)号：US20230026294A1

公开(公告)日：2023-01-26

申请号：US17652905

申请日：2022-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Sanjeev AGGARWAL

IPC: H03K19/1776 ,  G11C11/16 ,  G11C13/00 ,  H03K19/17724 ,  H03K19/17784

Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.

公开(公告)号：US20220291833A1

公开(公告)日：2022-09-15

申请号：US17201924

申请日：2021-03-15

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Cristian P. MASGRAS

IPC: G06F3/06

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

公开(公告)号：US20190213136A1

公开(公告)日：2019-07-11

申请号：US16359514

申请日：2019-03-20

Applicant: Everspin Technologies, Inc.

Inventor： Thomas S. ANDRE ,  Syed M. ALAM ,  Chitra K. SUBRAMANIAN ,  Javed S. BARKATULLAH

IPC: G06F12/0893 ,  G06F3/06 ,  G06F12/0862 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32 ,  G11C11/16 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0215 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2024 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272 ,  Y02D10/13

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US20190199375A1

公开(公告)日：2019-06-27

申请号：US16288664

申请日：2019-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Thomas ANDRE

IPC: H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1076

Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.

公开(公告)号：US20250068341A1

公开(公告)日：2025-02-27

申请号：US18590543

申请日：2024-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Michael SADD ,  Jacob T. WILLIAMS

IPC: G06F3/06

Abstract: Systems and techniques include identifying a network layer for performing a memory operation, identifying a subset of a plurality of configuration bit clusters of a non-volatile distributed memory that are mapped to the identified network layer using a cluster mapping, in response to identifying the subset of the plurality of configuration bit clusters, activating the subset of the plurality of configuration bit clusters, loading network component data from the subset of the plurality of configuration bit clusters into a local buffer, and applying the network component data to the network layer for performing the memory operation.

公开(公告)号：US20240304228A1

公开(公告)日：2024-09-12

申请号：US18668795

申请日：2024-05-20

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C7/1069 ,  G11C5/146 ,  G11C7/1045 ,  G11C7/1096

Abstract: 1. The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

公开(公告)号：US20240112713A1

公开(公告)日：2024-04-04

申请号：US18478643

申请日：2023-09-29

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jacob T. WILLIAMS

IPC: G11C11/16 ,  G01R31/3185 ,  H03K3/037

CPC classification number: G11C11/1675 ,  G01R31/318525 ,  G01R31/318536 ,  G01R31/318552 ,  G11C11/1673 ,  G11C11/1693 ,  H03K3/037 ,  H03K19/20

Abstract: A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.