公开(公告)号：US20160049399A1

公开(公告)日：2016-02-18

申请号：US14865784

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/28026 ,  H01L21/2807 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/105 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/772 ,  H01L29/7833 ,  H01L29/785

Abstract: One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers.

Abstract translation: 本文公开的晶体管器件的一个说明性栅极结构包括高k栅极绝缘层和位于高k栅极绝缘层上的功函数金属层。 该装置还包括位于功函数金属层上的第一体金属层。 该装置还包括第二体金属层。 第一和第二块体金属层具有基本上相同的高度水平的上表面，并且第一和第二块体金属层由基本上相同的材料制成。 该器件还包括在第一和第二块体金属层之间的导电蚀刻停止层。

公开(公告)号：US09263541B2

公开(公告)日：2016-02-16

申请号：US14261559

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L21/00 ,  H01L21/16 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract translation: 本发明的实施方案提供了用于硅锗（SiGe）或锗通道材料的高K电介质膜及其制造方法。 作为该方法的第一步，在半导体衬底上形成界面层（IL），提供降低的界面陷阱密度。 然而，使用超薄层作为阻挡膜，以避免高k膜中的锗扩散和从高k膜到界面层（IL）的氧扩散，因此，诸如氧化铝（Al 2 O 3）的介电膜， ，氧化锆或氧化镧（La 2 O 3）。 此外，这些电影可以提供高热预算。 然后在第一介电层上沉积第二介电层。 第二电介质层是高k电介质层，提供有效的氧化物厚度（EOT）降低，从而提高器件性能。

公开(公告)号：US09209135B2

公开(公告)日：2015-12-08

申请号：US14227807

申请日：2014-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy.

Abstract translation: 半导体器件包括限定在电介质层中的凹部，凹部具有延伸到凹部的上角部的上侧壁部分和在上侧壁部分下方的下侧壁部分。 互连结构定位在凹槽中。 互连结构包括连续的衬垫层，其具有分别位于上下侧壁部分的横向相邻的上层和下层部分。 上层部分包括第一过渡金属和第二过渡金属的合金，下层部分包括第二过渡金属，但不包括第一过渡金属。 互连结构还包括基本上填充凹部的填充材料，其中第二过渡金属对于填充材料具有比合金更高的润湿性。

公开(公告)号：US20150340497A1

公开(公告)日：2015-11-26

申请号：US14283636

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Naim Moumen ,  Chanro Park ,  William J. Taylor, JR.

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.

Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，执行外延沉积工艺以在器件的源极/漏极区域中的有源区上形成外延半导体材料，进行蚀刻 处理外延半导体材料以去除外延半导体材料的一部分，以便限定外延半导体材料中的至少一个外延凹部，在外延半导体材料的上表面上形成金属硅化物层，并且在至少一个 epi凹槽，并且形成导电耦合到金属硅化物层的导电结构。

公开(公告)号：US09142633B2

公开(公告)日：2015-09-22

申请号：US13714049

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Mark V. Raymond ,  Valli Arunachalam ,  Hoon Kim

IPC: H01L21/283 ,  H01L29/49 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4916 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括提供半导体衬底并在半导体衬底上形成翅片。 每个翅片形成有侧壁。 该方法还包括在每个翅片的侧壁上共形沉积金属膜堆叠。 在该方法中，金属膜堆叠被退火以在每个翅片的侧壁上形成金属硅化物膜。

公开(公告)号：US08932923B2

公开(公告)日：2015-01-13

申请号：US13770493

申请日：2013-02-19

Applicant: Globalfoundries, Inc.

Inventor： Hoon Kim ,  Kisik Choi

IPC: H01L21/8238 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.

Abstract translation: 具有NFET和PFET的半导体器件的栅极结构包括在NFET和PFET的栅极上方的基于铪的电介质的下层和镧系元素电介质的上层。 将电介质退火以将其混合在NFET上方，导致降低的功函数和相应的阈值电压降低。 在NFET栅极上方的混合电介质上的退火的较厚的氮化钛盖也降低了功函数和阈值电压。 在PFET栅极上的TiN盖和铪基电介质之上，是未经退火的另一层氮化钛。 钨的导电层覆盖该结构。

公开(公告)号：US08877633B2

公开(公告)日：2014-11-04

申请号：US13852084

申请日：2013-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76859 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier system comprised of at least one barrier material and at least two metallic elements, and performing a heating process to form a metal alloy comprised of the at least two metallic elements in the barrier system. Also disclosed is a device that comprises a trench/via in a layer of insulating material, a barrier system positioned in the trench/via, wherein the barrier system comprises at least one barrier material and a metal alloy comprised of at least two metallic elements that are comprised of materials other than the at least one barrier material, and a conductive structure positioned in the trench/via above the barrier system.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，形成由至少一种阻挡材料和至少两种金属元素组成的阻挡系统，并且进行加热工艺以形成由 屏障系统中至少有两个金属元素。 还公开了一种装置，其包括绝缘材料层中的沟槽/通孔，位于沟槽/通孔中的阻挡系统，其中阻挡系统包括至少一种阻挡材料和由至少两个金属元素组成的金属合金， 由至少一种阻挡材料以外的材料构成，以及位于屏障系统上方的沟槽/通孔中的导电结构。

公开(公告)号：US20190198381A1

公开(公告)日：2019-06-27

申请号：US16288780

申请日：2019-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/7682 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US20180122919A1

公开(公告)日：2018-05-03

申请号：US15337254

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/28026 ,  H01L21/3213 ,  H01L29/401 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/66795

Abstract: One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.

公开(公告)号：US20180033871A1

公开(公告)日：2018-02-01

申请号：US15219403

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/3086 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming channel semiconductor material for a nano-sheet device and a transistor device, forming a device gate insulation layer on both the nano-sheet device and on the transistor device, and forming first and second sacrificial gate structures for the nano-sheet device and the transistor device. In this example, the method also includes removing the sacrificial gate structures so as to define, respectively, first and second gate cavities, wherein the device gate insulation layer is exposed within each of the gate cavities, removing the device gate insulation layer for the transistor device from within the first gate cavity while leaving the device gate insulation layer in position within the second gate cavity, and forming first and second replacement gate structures in the first and second gate cavities, respectively.