公开(公告)号：US20190123005A1

公开(公告)日：2019-04-25

申请号：US15793130

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald Gene Filippi, JR.

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/308

CPC classification number: H01L24/05 ,  H01L21/3081 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/0556 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462

Abstract: The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.

公开(公告)号：US09435852B1

公开(公告)日：2016-09-06

申请号：US14862587

申请日：2015-09-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrew T. Kim ,  Cathryn J. Christiansen ,  Ping-Chuan Wang

IPC: H01L23/48 ,  G01R31/28 ,  H01L23/528 ,  H01L23/522 ,  H01L21/66

CPC classification number: G01R31/2884 ,  H01L22/34

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.

Abstract translation: 本公开的方面提供了集成电路（IC）测试结构。 根据本公开的IC结构可以包括：监视器链，其具有通过多个金属线电连接到第二端的第一端，每条金属线位于第一金属层和第二金属层之一内，其中第一金属层 与第二金属层垂直分离; 第一测试线定位在第一金属水平面内并沿第一方向延伸，其中第一测试线与监视器链电绝缘; 以及第二测试线，其位于所述第二金属层内并且在第二方向上延伸，其中所述第二测试线与所述监视器链和所述第一测试线电绝缘，并且其中所述第一方向与所述第二方向不同。

公开(公告)号：US20160071742A1

公开(公告)日：2016-03-10

申请号：US14942228

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/32139 ,  G09C1/00 ,  H01L21/0273 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76885 ,  H01L22/34 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/57 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2224/05097 ,  H04L9/3278 ,  H04L2209/12

Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.

公开(公告)号：US10388617B2

公开(公告)日：2019-08-20

申请号：US15793130

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald Gene Filippi, Jr.

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/308 ,  H01L21/60

Abstract: The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.

公开(公告)号：US10325862B2

公开(公告)日：2019-06-18

申请号：US15657666

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

公开(公告)号：US10297546B2

公开(公告)日：2019-05-21

申请号：US15652594

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erdem Kaltalioglu ,  Ronald G. Filippi, Jr. ,  Ping-Chuan Wang ,  Cathryn Christiansen

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/522 ,  H01L21/306

Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.

公开(公告)号：US20170317166A1

公开(公告)日：2017-11-02

申请号：US15142838

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Hanyi Ding ,  Ping-Chuan Wang ,  Kai D. Feng

IPC: H01L29/06 ,  H01L21/76 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/762

CPC classification number: H01L21/32051 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/76229

Abstract: Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.

公开(公告)号：US20170316986A1

公开(公告)日：2017-11-02

申请号：US15140025

申请日：2016-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Ping-Chuan Wang ,  Kai D. Feng

IPC: H01L21/84 ,  H01L21/28 ,  H01L21/3065 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.

公开(公告)号：US20170242067A1

公开(公告)日：2017-08-24

申请号：US15048704

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ping-Chuan Wang ,  Andrew T. Kim ,  Ronald G. Filippi

IPC: G01R31/28 ,  H01L23/522 ,  H01L27/08 ,  H01L21/66

CPC classification number: G01R31/2858 ,  H01L22/34 ,  H01L23/5226 ,  H01L27/0802

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

公开(公告)号：US09318413B2

公开(公告)日：2016-04-19

申请号：US14065451

申请日：2013-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fen Chen ,  Andrew T. Kim ,  Minhua Lu ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76849 ,  H01L21/76898 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC structure according to embodiments of the present invention may include a through-semiconductor via (TSV) embedded within a substrate, the TSV having an axial end; and a metal cap contacting the axial end of the TSV, wherein the metal cap has a greater electrical resistivity than the TSV.

Abstract translation: 本公开通常提供具有TSV的集成电路（IC）结构以及制造IC结构和TSV的方法。 根据本发明的实施例的IC结构可以包括嵌入在基板内的贯穿半导体通孔（TSV），TSV具有轴向端; 以及与TSV的轴向端接触的金属盖，其中金属帽具有比TSV更大的电阻率。