公开(公告)号：US09368578B2

公开(公告)日：2016-06-14

申请号：US13758225

申请日：2013-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

IPC: H01L29/66 ,  H01L29/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/12 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211

Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.

Abstract translation: 在第一和第二层之间获得由第一半导体材料的第一和第二层和应变释放缓冲层（SRB）层组成的结构，在第二层的开口的侧壁上形成侧壁间隔物，并形成第三半导体 所述开口中的材料，其中所述第一，第二和第三半导体材料是不同的。 一种器件包括第一和第二层第一和第二半导体材料以及位于第一层之上的SRB层。 第二层位于SRB层的第一部分之上，第三半导体材料的区域位于第二层的开口中并且位于SRB层的第二部分之上，并且绝缘材料位于由 第三半导体材料和第二层。

公开(公告)号：US09293324B2

公开(公告)日：2016-03-22

申请号：US14274406

申请日：2014-05-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Steven Bentley ,  Ajey P. Jacob

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L21/02538 ,  H01L29/20 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices including a fin and method of forming the semiconductor devices are provided herein. In an embodiment, a method of forming a semiconductor device includes forming a fin overlying a semiconductor substrate. The fin is formed by epitaxially-growing a semiconductor material over the semiconductor substrate, and the fin has a first portion that is proximal to the semiconductor substrate and a second portion that is spaced from the semiconductor substrate by the first portion. A gate structure is formed over the fin and the semiconductor substrate. The first portion of the fin is etched to form a gap between the second portion and the semiconductor substrate.

Abstract translation: 本文提供了包括翅片的半导体器件和形成半导体器件的方法。 在一个实施例中，形成半导体器件的方法包括形成覆盖半导体衬底的散热片。 鳍状物通过在半导体衬底上外延生长半导体材料而形成，并且鳍具有靠近半导体衬底的第一部分和通过第一部分与半导体衬底间隔开的第二部分。 在鳍片和半导体衬底上形成栅极结构。 蚀刻鳍的第一部分以在第二部分和半导体衬底之间形成间隙。

公开(公告)号：US20150140761A1

公开(公告)日：2015-05-21

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/266 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US11201152B2

公开(公告)日：2021-12-14

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/51

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US10446451B1

公开(公告)日：2019-10-15

申请号：US16027834

申请日：2018-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Soss ,  Steven Bentley

IPC: H01L21/8238 ,  H01L29/08 ,  H01L21/768 ,  H01L29/66

Abstract: The present disclosure is directed to various embodiments of a method for forming replacement gate structures for vertical transistors. One illustrative method disclosed herein includes, among other things, forming first and second vertical semiconductor structures, forming first and second sacrificial spacers adjacent channel regions of the first and second vertical semiconductor structures, respectively, forming a ring spacer adjacent the first and second sacrificial spacers, removing end portions of the ring spacer to expose end portions of the first and second sacrificial spacers, replacing the first sacrificial spacer with a first replacement gate structure including a first gate insulation layer and a first conductive gate material, replacing the second sacrificial spacer with a second replacement gate structure including a second gate insulation layer and a second conductive gate material, removing remaining portions of the ring spacer to define a spacer cavity, and forming a dielectric material in the spacer cavity.

公开(公告)号：US20190312116A1

公开(公告)日：2019-10-10

申请号：US15947991

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Steven Bentley

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

公开(公告)号：US10312154B2

公开(公告)日：2019-06-04

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8234

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20190088767A1

公开(公告)日：2019-03-21

申请号：US15709500

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Hui Zang ,  Steven Bentley

IPC: H01L29/66

Abstract: Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.

公开(公告)号：US20190035938A1

公开(公告)日：2019-01-31

申请号：US15662526

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.

公开(公告)号：US20180366372A1

公开(公告)日：2018-12-20

申请号：US15626321

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet H. Suvarna ,  Steven Bentley ,  Mark V. Raymond ,  Peter M. Zeitzoff

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/45 ,  H01L29/78 ,  H01L29/08

Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.