公开(公告)号：US09859382B2

公开(公告)日：2018-01-02

申请号：US14959825

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/267 ,  H01L25/00 ,  H01L25/065 ,  H01L29/20 ,  H01L29/161 ,  H01L27/092 ,  H01L29/737

CPC classification number: H01L29/267 ,  H01L21/8258 ,  H01L23/3114 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/737 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2224/83

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

公开(公告)号：US20170365695A1

公开(公告)日：2017-12-21

申请号：US15187860

申请日：2016-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L29/737 ,  H01L21/8228 ,  H01L21/8226 ,  H01L29/04 ,  H03F3/213 ,  H01L21/8222 ,  H01L29/165 ,  H01L29/161 ,  H01L27/082 ,  H01L29/66

CPC classification number: H01L29/7378 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0823 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7371 ,  H03F3/213 ,  H03F2200/294

Abstract: Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

公开(公告)号：US09847408B1

公开(公告)日：2017-12-19

申请号：US15187860

申请日：2016-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L21/331 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/66 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165 ,  H01L29/04 ,  H01L21/8222 ,  H03F3/213 ,  H01L21/8226

CPC classification number: H01L29/7378 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0823 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7371 ,  H03F3/213 ,  H03F2200/294

Abstract: Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

公开(公告)号：US09825157B1

公开(公告)日：2017-11-21

申请号：US15196920

申请日：2016-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata A. Camillo-Castillo ,  Anthony K. Stamper

IPC: H01L29/73 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor with a stress component and methods of manufacture. The heterojunction bipolar transistor includes a collector region, an emitter region and a base region. Stress material is formed within a trench of a substrate and surrounding at least the collector region and the base region.

公开(公告)号：US20170162656A1

公开(公告)日：2017-06-08

申请号：US14959825

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/267 ,  H01L25/00 ,  H01L29/737 ,  H01L29/161 ,  H01L27/092 ,  H01L25/065 ,  H01L29/20

CPC classification number: H01L29/267 ,  H01L21/8258 ,  H01L23/3114 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/737 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2224/83

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

公开(公告)号：US09583569B2

公开(公告)日：2017-02-28

申请号：US14968286

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/73 ,  H01L29/08 ,  H01L29/732 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/737 ,  H01L29/10

CPC classification number: H01L29/0826 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/7378

Abstract: Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.

Abstract translation: 双极结型晶体管的器件结构。 在衬底的顶表面上形成一层。 在该层中形成沟槽并且具有多个侧壁，其宽度在相对的一对侧壁之间的宽度随着距离衬底顶表面的距离的增加而变化。 在沟槽中形成双极结型晶体管的集电极基座。

公开(公告)号：US20160380088A1

公开(公告)日：2016-12-29

申请号：US14747668

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Marwan H. Khater

IPC: H01L29/737 ,  H01L21/762 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/764

CPC classification number: H01L29/7371 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732

Abstract: Device structure and fabrication methods for a bipolar junction transistor. A trench isolation region is formed that bounds an active device region along a sidewall. A dielectric region is formed that extends laterally from the sidewall of the active device region into the active device region. The dielectric region is located beneath a top surface of the active device region such that a section of the active device region is located between the top surface and the dielectric region.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 形成沿着侧壁界定有源器件区域的沟槽隔离区域。 形成了从有源器件区域的侧壁横向延伸到有源器件区域中的电介质区域。 电介质区域位于有源器件区域的顶表面之下，使得有源器件区域的一部分位于顶表面和电介质区域之间。

公开(公告)号：US20160211345A1

公开(公告)日：2016-07-21

申请号：US14601655

申请日：2015-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/73 ,  H01L29/08 ,  H01L21/306

CPC classification number: H01L29/66234 ,  H01L21/306 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.

Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 在基板上形成第一半导体层，在第一半导体层上形成第二半导体层。 蚀刻第一半导体层，第二半导体层和衬底以限定来自第二半导体层的第一和第二发射极指状物以及横向位于第一和第二发射极指之间的衬底中的沟槽。 第一半导体层可以用作器件结构中的基层。

公开(公告)号：US09318584B2

公开(公告)日：2016-04-19

申请号：US14492582

申请日：2014-09-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Robert K. Leidy ,  Qizhi Liu

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L21/762

CPC classification number: H01L29/732 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 器件结构包括衬底中的集电极区域，延伸到衬底中并由电绝缘体构成的多个隔离结构以及衬底中的隔离区域。 隔离结构具有长度并且以横向于长度的间距布置，使得每个相邻的一对隔离结构被基板的相应部分分开。 隔离区域通过集电区域的第一部分与隔离结构中的至少一个横向分离。 隔离区域将收集区域的第二部分与收集器区域的第一部分横向分离。 器件结构还包括在集电极区域的第二部分上的本征基极和在本征基极上的发射极。 发射极相对于隔离结构的长度具有横向定向的长度。

公开(公告)号：US20160087073A1

公开(公告)日：2016-03-24

申请号：US14958345

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/66242 ,  H01L29/0649 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.