公开(公告)号：US10157789B2

公开(公告)日：2018-12-18

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

公开(公告)号：US20180337045A1

公开(公告)日：2018-11-22

申请号：US15597277

申请日：2017-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Ruilong Xie ,  Wenhui Wang ,  Yulu Chen ,  Erik Verduijn ,  Zhengqing John Qi ,  Guoxiang Ning ,  Daniel J. Dechene

IPC: H01L21/033 ,  H01L23/528 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/027

CPC classification number: H01L21/0276 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76879

Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.

公开(公告)号：US20180102354A1

公开(公告)日：2018-04-12

申请号：US15289401

申请日：2016-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yan Wang ,  Jia Zeng ,  Chenchen Wang ,  Wenhui Wang ,  Lei Yuan ,  Jongwook Kye

IPC: H01L27/02 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L21/76838

Abstract: At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.

公开(公告)号：US09651855B2

公开(公告)日：2017-05-16

申请号：US14685701

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lei Sun ,  Wenhui Wang ,  Ryan Ryoung-Han Kim

IPC: G03F1/22 ,  G03F1/36 ,  G06F17/50 ,  H01L21/027 ,  G03F7/20

CPC classification number: G03F1/22 ,  G03F1/36 ,  G03F7/2045 ,  G06F17/5081 ,  H01L21/0274

Abstract: A method of optical proximity correction (OPC) in extreme ultraviolet lithography (EUV) lithography includes providing a patterned layout design including first and second design polygons that correspond with the pre-pattern opening, wherein the first and second design polygons are separated by a separation distance, and correcting the patterned layout design using OPC by generating (1) a third polygon that has dimensions corresponding to a combination of the first and second design polygons and the separation distance and (2) and filled polygon within the third polygon, thereby generating an OPC-corrected patterned layout design. EUV photomasks may be manufactured from the OPC-corrected patterned layout design, and integrated circuits may be fabricated using such EUV photomasks.

公开(公告)号：US20160336225A1

公开(公告)日：2016-11-17

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US20160162624A1

公开(公告)日：2016-06-09

申请号：US14685701

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lei Sun ,  Wenhui Wang ,  Ryan Ryoung-Han Kim

IPC: G06F17/50 ,  G03F1/22 ,  G03F1/70 ,  H01L21/027

CPC classification number: G03F1/22 ,  G03F1/36 ,  G03F7/2045 ,  G06F17/5081 ,  H01L21/0274

Abstract: A method of optical proximity correction (OPC) in extreme ultraviolet lithography (EUV) lithography includes providing a patterned layout design including first and second design polygons that correspond with the pre-pattern opening, wherein the first and second design polygons are separated by a separation distance, and correcting the patterned layout design using OPC by generating (1) a third polygon that has dimensions corresponding to a combination of the first and second design polygons and the separation distance and (2) and filled polygon within the third polygon, thereby generating an OPC-corrected patterned layout design. EUV photomasks may be manufactured from the OPC-corrected patterned layout design, and integrated circuits may be fabricated using such EUV photomasks.

Abstract translation: 在极紫外光刻（EUV）光刻中的光学邻近校正（OPC）的方法包括提供图案化布局设计，其包括与预图案开口对应的第一和第二设计多边形，其中第一和第二设计多边形通过分离 距离，并且通过生成（1）具有对应于第一和第二设计多边形和分离距离的组合的尺寸的第三多边形以及（2）和第三多边形内的填充多边形来校正图案化布局设计，从而生成 OPC校正图案布局设计。 EUV光掩模可以由OPC校正的图案化布局设计制造，并且可以使用这种EUV光掩模来制造集成电路。

公开(公告)号：US09140975B2

公开(公告)日：2015-09-22

申请号：US14106219

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Chanro Park ,  Wenhui Wang ,  Hui Zang

IPC: G03F1/62 ,  G03F1/64 ,  G03F1/00 ,  G03F1/22

CPC classification number: G03F1/142 ,  G03F1/22 ,  G03F1/62 ,  G03F1/64

Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.

Abstract translation: 公开了一种在由掩模和防护薄膜组成的区域与掩模和防护薄膜之间的区域以及所得到的装置之间形成改进的EUV掩模和防护薄膜组件的方法。 实施例包括在EUV掩模上的图案化区域周围形成框架; 在框架上形成膜; 并在框架中形成孔。

公开(公告)号：US09093302B2

公开(公告)日：2015-07-28

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。