公开(公告)号：US20120329269A1

公开(公告)日：2012-12-27

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US20120104610A1

公开(公告)日：2012-05-03

申请号：US12915510

申请日：2010-10-29

申请人： Ronald Filippi ,  Ping-Chuan Wang ,  Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Andrew H. Simon

发明人： Ronald Filippi ,  Ping-Chuan Wang ,  Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Andrew H. Simon

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

摘要翻译： 一种改进的互连结构，其包括具有嵌入其中的导电特征的介电层，所述导电特征具有与介电层的第二顶表面基本共面的第一顶表面; 金属盖层直接位于第一顶表面上，其中金属盖层基本上不延伸到第二顶表面上; 位于所述第二顶表面上的第一电介质盖层，其中所述第一电介质盖层基本上不延伸到所述第一顶表面上，并且所述第一电介质盖层比所述金属盖层厚; 以及金属盖层和第一电介质盖层上的第二电介质盖层。 还提供了形成互连结构的方法。

公开(公告)号：US07795740B2

公开(公告)日：2010-09-14

申请号：US12245133

申请日：2008-10-03

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。 根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使处理后的表面变得疏水的处理步骤。 在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。

公开(公告)号：US07776737B2

公开(公告)日：2010-08-17

申请号：US12191534

申请日：2008-08-14

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

IPC分类号： H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76816 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.

摘要翻译： 一种集成电路，其包括半导体衬底，所述半导体衬底上的包括金属布线的第一金属布线级别，所述第一金属布线层上的互连布线级别，其包括层间电介质内的通孔布线，第二金属布线级别 包括金属布线的互连布线层，至少一个具有多个介电填充形状的金属布线，其减小了所述至少一个金属布线的横截面积，并且其中所述通孔互连使金属线 在第一布线级别和第二布线级中的至少一个金属布线中，通孔布线与多个介质填充形状相邻并间隔开。 还公开了一种方法，其中多个介电填充形状被放置成与第二布线层中的布线中的通孔接触区域相邻并间隔开。

公开(公告)号：US20080173985A1

公开(公告)日：2008-07-24

申请号：US11626552

申请日：2007-01-24

申请人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son Van Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

发明人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son Van Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

IPC分类号： H01L23/58 ,  H01L21/318

CPC分类号： H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

摘要： A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability,

摘要翻译： 公开了介电盖和相关方法。 在一个实施例中，电介质盖包括具有光学带隙（例如大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。 电介质盖表现出高模量，并且在ULK UV固化处理后稳定，例如：铜低k后端（BEOL）纳米电子器件，导致更少的膜和器件开裂和改善的可靠性，

公开(公告)号：US20070284736A1

公开(公告)日：2007-12-13

申请号：US11419077

申请日：2006-05-18

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Shyng-Tsong Chen ,  Kelly Malone

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Shyng-Tsong Chen ,  Kelly Malone

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5226 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

摘要翻译： 本发明提供了一种改进的可靠性的互连结构。 本发明的互连结构具有增强的由嵌入式金属衬垫提供的通孔触点的机械强度。 嵌入的金属衬垫可以是连续的或不连续的。 不连续的嵌入式金属衬垫由位于层间介质层内的通孔底部的不连续界面提供。

公开(公告)号：US20070273044A1

公开(公告)日：2007-11-29

申请号：US11440984

申请日：2006-05-25

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。 根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使处理后的表面变得疏水的处理步骤。 在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。

公开(公告)号：US20150137312A1

公开(公告)日：2015-05-21

申请号：US14580539

申请日：2014-12-23

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali Lustig ,  Andrew H. Simon ,  Junjing Bao

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali Lustig ,  Andrew H. Simon ,  Junjing Bao

IPC分类号： H01L23/525 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L23/5256 ,  H01H69/02 ,  H01H85/046 ,  H01H2085/0275 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

摘要： Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.

摘要翻译： 提供更可靠的保险丝熔断位置的结构及其制作方法。 在熔断器熔断之前，垂直金属保险丝熔断结构在熔丝导体有意损坏的部分。 损坏的部分有助于熔断器在已知位置中熔断，从而降低后吹回路中的电阻变化。 同时，在保险丝熔断之前，保险丝结构能够正常工作。 熔丝导体的损坏部分是通过在保险丝导体的一部分上方的盖层中形成开口，并蚀刻熔丝导体而制成的。 优选地，开口对准，使得损坏部分在熔丝导体的顶角上。 可以在与损坏的保险丝导体相邻的绝缘体中形成空腔。 具有空腔的损坏的保险丝结构可以容易地结合在制造具有气隙的集成电路的过程中。

公开(公告)号：US20130049207A1

公开(公告)日：2013-02-28

申请号：US13221698

申请日：2011-08-30

申请人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephan A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

发明人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephan A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

IPC分类号： H01L21/26 ,  H01L23/485 ,  H01L21/66

CPC分类号： H01L21/3105 ,  H01L21/76828 ,  H01L21/76829 ,  H01L22/14

摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。

公开(公告)号：US08298948B2

公开(公告)日：2012-10-30

申请号：US12613551

申请日：2009-11-06

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/302

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

摘要翻译： 一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上， 并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积 铜线除去杂散金属材料。